-
公开(公告)号：US07358555B2
公开(公告)日：2008-04-15
申请号：US11409040
申请日：2006-04-24
IPC分类号： H01L27/108
CPC分类号： H01L27/0811 , H01L27/1203
摘要： While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered.Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.
摘要翻译： 在提高去耦电容器的频率特性的同时，抑制源极线路的电压降并使其稳定，从而提供抑制去耦电容器布置的面积效率下降的半导体器件。 去耦电容器DM1和DM2连接在连接到用于为电路块C 1供电的高速电路的焊盘的源极线和连接到接地焊盘的地线之间，并且用于高速的电容器阵列 形成电路。 多个去耦电容器DM1连接在连接到用于向电路块C 2供电的低速电路的焊盘的源极线和连接到接地焊盘的地线之间，以及用于低速的电容器阵列 形成电路。 去耦电容器DM 1的栅电极尺寸与DM2不同。
-
公开(公告)号：US20060237726A1
公开(公告)日：2006-10-26
申请号：US11409040
申请日：2006-04-24
IPC分类号： H01L29/04
CPC分类号： H01L27/0811 , H01L27/1203
摘要： While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.
摘要翻译： 在提高去耦电容器的频率特性的同时，抑制源极线路的电压降并使其稳定，从而提供抑制去耦电容器布置的面积效率下降的半导体器件。 去耦电容器DM1和DM2连接在连接到用于为电路块C 1供电的高速电路的焊盘的源极线和连接到接地焊盘的地线之间，并且用于高速的电容器阵列 形成电路。 多个去耦电容器DM1连接在连接到用于向电路块C 2供电的低速电路的焊盘的源极线和连接到接地焊盘的地线之间，以及用于低速的电容器阵列 形成电路。 去耦电容器DM 1的栅电极尺寸与DM2不同。
-
公开(公告)号：US20060043494A1
公开(公告)日：2006-03-02
申请号：US11210666
申请日：2005-08-25
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/84
摘要： A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.
摘要翻译： 在SOI层和触点之间的连接处（即，在元件隔离绝缘膜下）形成肖特基结，而不形成具有高杂质浓度的P + +区域。 身体接触的表面提供阻挡金属。 作为阻挡金属和SOI层的反应的结果，在本体接触和SOI层之间形成硅化物。
-
公开(公告)号：US06914307B2
公开(公告)日：2005-07-05
申请号：US10657068
申请日：2003-09-09
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
IPC分类号： H01L21/76 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/12 , H01L29/45 , H01L29/786 , H01L29/76
CPC分类号： H01L21/76286 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/458
摘要： A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.
摘要翻译： 半导体器件包括半导体层，形成在半导体层上的多个半导体元件和设置在半导体层的表面中的隔离膜，半导体元件通过隔离膜彼此电隔离。 半导体器件还包括设置在隔离膜下方并由半导体层中由不同导电类型的两个半导体区域形成的PN结部分。 隔离膜包括设置在与PN结部分的顶部相对应的位置的氮化物膜，并且在两个半导体区域上具有基本上均匀的厚度，以及设置在上部和下部的上部氧化物膜和低级氧化物膜 氮化膜。 半导体层的表面在隔离膜的表面露出的状态下被硅化。
-
公开(公告)号：US06310377B1
公开(公告)日：2001-10-30
申请号：US09134896
申请日：1998-08-17
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Il Jung Kim , Yasuo Inoue , Shigeto Maegawa , Takashi Ipposhi
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Il Jung Kim , Yasuo Inoue , Shigeto Maegawa , Takashi Ipposhi
IPC分类号： H01L2701
CPC分类号： H01L21/76202 , H01L21/76264 , H01L21/76281 , H01L21/76291 , H01L27/11807 , H01L27/1203
摘要： FS-isolated fields (10a, 10b). LOCOS-isolated fields (11c, 11d). FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can he provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.
摘要翻译： FS隔离场（10a，10b）。 LOCOS隔离场（11c，11d）。 FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i）按此顺序排列。 因此，可以提供主布局，其中将具有被提供固定电位的主体和具有不具有固定电位的主体的SOI晶体管混合。
-
公开(公告)号：US07541644B2
公开(公告)日：2009-06-02
申请号：US10793841
申请日：2004-03-08
IPC分类号： H01L29/72
CPC分类号： H01L23/481 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L29/78639 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).
摘要翻译： 半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。 在SOI层（12）中形成晶体管（T1）。 布线（17a）通过接触插塞（15a）与晶体管（T1）的源极连接。 背衬金属（18）形成在支撑基板（10）的下表面（背面）上，背面金属（18）通过散热塞（16）与布线17a连接。 接触插头（15a），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比硅的热导率更高的导热性 氧化膜（11）和支撑基板（10）。
-
公开(公告)号：US5808341A
公开(公告)日：1998-09-15
申请号：US747933
申请日：1996-11-12
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Il Jung Kim , Yasuo Inoue , Shigeto Maegawa , Takashi Ipposhi
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Il Jung Kim , Yasuo Inoue , Shigeto Maegawa , Takashi Ipposhi
IPC分类号： H01L21/762 , H01L21/82 , H01L27/118 , H01L27/12 , H01L29/786 , H01L29/00
CPC分类号： H01L21/76202 , H01L21/76264 , H01L27/11807 , H01L27/1203 , H01L21/76281 , H01L21/76291
摘要： FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.
摘要翻译： FS隔离场（10a，10b），LOCOS隔离场（11c，11d），FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i） 这个命令。 因此，可以提供主布局，其中将具有被提供固定电位的体的SOI晶体管和具有不具有固定电位的体的SOI晶体管混合。
-
公开(公告)号：US20070007595A1
公开(公告)日：2007-01-11
申请号：US11520640
申请日：2006-09-14
IPC分类号： H01L27/12
CPC分类号： H01L23/481 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L29/78639 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).
摘要翻译： 半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。 在SOI层（12）中形成晶体管（T 1）。 布线（17a）通过接触插塞（15A）与晶体管（T 1）的源极连接。 背衬金属（18）形成在支撑基板（10）的下表面（背面）上，所述背金属（18）通过散热塞（16）与布线（17a）连接。 接触塞（15A），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比 氧化硅膜（11）和支撑基板（10）。
-
29.发明授权Method of manufacturing semiconductor device having impurity region under isolation region 有权制造在隔离区域具有杂质区域的半导体器件的制造方法公开(公告)号：US07105389B2
公开(公告)日：2006-09-12
申请号：US10748273
申请日：2003-12-31
IPC分类号： H01L21/00
CPC分类号： H01L29/78615 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
摘要翻译： 在形成NMOS晶体管的源极/漏极区域的情况下，在N + +块区域中的N + +块区域<41>的栅极方向延伸区域 抗蚀膜<51 <防止位于栅极方向延伸区域<41a>下方的阱区11从注入N型杂质。 具有在栅电极9的纵向延伸上注入N型杂质的可能性的阱区<11>的高电阻形成区域可以形成为高电阻形成区域 比传统的高电阻形成区域窄。 因此，获得具有能够降低体电阻的部分隔离体固定的SOI结构的半导体器件及其制造方法。
-
公开(公告)号：US06335267B1
公开(公告)日：2002-01-01
申请号：US09667498
申请日：2000-09-22
IPC分类号： H01L2120
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.
摘要翻译： 提供半导体衬底和制造半导体器件的方法。 氧化膜（13）通过氧化SOI衬底（10）的边缘部分和下主表面而形成。 通过使用暴露在SOI衬底（10）的边缘部分和下部主表面上的氧化膜（11）作为下面的氧化膜，以类似于LOCOS（硅的局部氧化物）氧化的方式进行该氧化步骤。 然后，氧化膜（13）的厚度大于SOI衬底（10）的边缘部分和下主表面上的氧化物膜（11）的厚度。 半导体衬底防止在其边缘处产生灰尘颗粒。
-
-
-
-
-
-
-
-
-
搜索结果
156 条记录 (耗时 0.028 秒)
