公开(公告)号：US5808341A

公开(公告)日：1998-09-15

申请号：US747933

申请日：1996-11-12

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

IPC分类号： H01L21/762 ,  H01L21/82 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L27/11807 ,  H01L27/1203 ,  H01L21/76281 ,  H01L21/76291

摘要： FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

摘要翻译： FS隔离场（10a，10b），LOCOS隔离场（11c，11d），FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i） 这个命令。 因此，可以提供主布局，其中将具有被提供固定电位的体的SOI晶体管和具有不具有固定电位的体的SOI晶体管混合。

公开(公告)号：US06310377B1

公开(公告)日：2001-10-30

申请号：US09134896

申请日：1998-08-17

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

IPC分类号： H01L2701

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76291 ,  H01L27/11807 ,  H01L27/1203

摘要： FS-isolated fields (10a, 10b). LOCOS-isolated fields (11c, 11d). FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can he provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

摘要翻译： FS隔离场（10a，10b）。 LOCOS隔离场（11c，11d）。 FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i）按此顺序排列。 因此，可以提供主布局，其中将具有被提供固定电位的主体和具有不具有固定电位的主体的SOI晶体管混合。

公开(公告)号：US06869865B2

公开(公告)日：2005-03-22

申请号：US10608154

申请日：2003-06-30

申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Kazunobu Ohta ,  Yasuo Inoue ,  Masanobu Kohara ,  Takashi Eura ,  Natsuro Tsubouchi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Kazunobu Ohta ,  Yasuo Inoue ,  Masanobu Kohara ,  Takashi Eura ,  Natsuro Tsubouchi

IPC分类号： H01L21/28 ,  H01L21/20 ,  H01L21/265 ,  H01L21/268 ,  H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L21/425

CPC分类号： H01L21/268 ,  H01L21/2652 ,  H01L21/28518 ,  H01L29/6659

摘要： Activation of impurities is achieved without involving creation of a crystal defect or deformation by using phonon absorption. A laser beam (42) having a wavelength in a range of 16 to 17 μm is irradiated onto silicon, to cause phonon absorption. Before an energy supplied from the laser beam (42) diffuses around a portion which is irradiated with the laser beam (42), solid phase epitaxy in the portion finishes. Accordingly, crystallization occurs only in the portion which is irradiated with the laser beam (42), and does not occur in a portion which is not irradiated with the laser beam (42). Hence, heat is not excessively absorbed. Also, local phase change such as melting and solidification is not caused.

摘要翻译： 实现杂质的活化而不涉及通过使用声子吸收产生晶体缺陷或变形。 将具有16至17μm波长范围的激光束（42）照射到硅上以引起声子吸收。 在从激光束（42）供给的能量在激光束（42）的一部分附近扩散之前，该部分的固相外延结束。 因此，仅在被激光束（42）照射的部分中发生结晶，不会发生在不被激光束（42）照射的部分。 因此，热量不会被过度吸收。 此外，不会引起局部相变，如熔化和凝固。

公开(公告)号：US06303425B1

公开(公告)日：2001-10-16

申请号：US09660448

申请日：2000-09-12

申请人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

IPC分类号： H01L218242

CPC分类号： H01L27/10823 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/78642

摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

摘要翻译： 第一杂质扩散层形成源极/漏极区之一并且还形成位线。 形成源极/漏极区域中的另一个并且还形成存储节点的第一半导体层，沟道半导体层和第二半导体层设置在第一杂质扩散层上。 电容绝缘膜设置在第二导电层上。 电池板设置在存储节点上，其间具有电容器绝缘膜。 位线的电容减小，并且由此构成的动态随机存取存储器执行高速操作。

公开(公告)号：US6150688A

公开(公告)日：2000-11-21

申请号：US38981

申请日：1998-03-12

申请人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

IPC分类号： H01L27/10 ,  H01L21/77 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/72

CPC分类号： H01L27/10823 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/78642

摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

公开(公告)号：US5780888A

公开(公告)日：1998-07-14

申请号：US758841

申请日：1996-12-02

申请人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

IPC分类号： H01L27/10 ,  H01L21/77 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10823 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/78642

摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

摘要翻译： 第一杂质扩散层形成源极/漏极区之一并且还形成位线。 形成源极/漏极区域中的另一个并且还形成存储节点的第一半导体层，沟道半导体层和第二半导体层设置在第一杂质扩散层上。 电容绝缘膜设置在第二导电层上。 电池板设置在存储节点上，其间具有电容器绝缘膜。 位线的电容减小，并且由此构成的动态随机存取存储器执行高速操作。

公开(公告)号：US5627390A

公开(公告)日：1997-05-06

申请号：US648828

申请日：1996-05-16

申请人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

IPC分类号： H01L27/10 ,  H01L21/77 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10823 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/78642

摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

摘要翻译： 第一杂质扩散层形成源极/漏极区之一并且还形成位线。 形成源极/漏极区域中的另一个并且还形成存储节点的第一半导体层，沟道半导体层和第二半导体层设置在第一杂质扩散层上。 电容绝缘膜设置在第二导电层上。 电池板设置在存储节点上，其间具有电容器绝缘膜。 位线的电容减小，并且由此构成的动态随机存取存储器执行高速操作。

公开(公告)号：US06383860B2

公开(公告)日：2002-05-07

申请号：US09908607

申请日：2001-07-20

申请人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

IPC分类号： H01L218242

CPC分类号： H01L27/10823 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/78642

摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

摘要翻译： 第一杂质扩散层形成源极/漏极区之一并且还形成位线。 形成源极/漏极区域中的另一个并且还形成存储节点的第一半导体层，沟道半导体层和第二半导体层设置在第一杂质扩散层上。 电容绝缘膜设置在第二导电层上。 电池板设置在存储节点上，其间具有电容器绝缘膜。 位线的电容减小，并且由此构成的动态随机存取存储器执行高速操作。

公开(公告)号：US5736438A

公开(公告)日：1998-04-07

申请号：US483411

申请日：1995-06-07

申请人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

发明人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L27/11 ,  H01L27/1108 ,  H01L29/78654 ,  H01L27/1281 ,  Y10S257/903

摘要： In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

摘要翻译： 在TFT负载型的小型化的完全CMOS SRAM中，场效应薄膜晶体管（TFT）能够实现对存储单元的稳定的读/写操作并且可以降低其功耗。 形成在绝缘体上的场效应薄膜晶体管包括有源层和栅电极。 栅电极形成在有源层的沟道区上，其间具有栅极绝缘膜。 有源层由沟道区和源极/漏极区形成。 沟道区由单晶硅层形成，不包含晶界。 源/漏区由多晶硅层形成。 沟道区域的晶体缺陷密度小于109个/ cm 2。 薄膜晶体管的通道宽度为1μm，导通电流为0.25μA/μm，OFF电流为15fA /μm。 薄膜晶体管可以被施加到用作CMOS型SRAM的存储单元中的负载晶体管的p沟道MOS晶体管。

公开(公告)号：US5514880A

公开(公告)日：1996-05-07

申请号：US142564

申请日：1993-10-28

申请人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

发明人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L27/11 ,  H01L27/1108 ,  H01L29/78654 ,  H01L27/1281 ,  Y10S257/903

摘要： In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

摘要翻译： 在TFT负载型的小型化的完全CMOS SRAM中，场效应薄膜晶体管（TFT）能够实现对存储单元的稳定的读/写操作并且可以降低其功耗。 形成在绝缘体上的场效应薄膜晶体管包括有源层和栅电极。 栅电极形成在有源层的沟道区上，其间具有栅极绝缘膜。 有源层由沟道区和源极/漏极区形成。 沟道区由单晶硅层形成，不包含晶界。 源/漏区由多晶硅层形成。 沟道区域的晶体缺陷密度小于109个/ cm 2。 薄膜晶体管的通道宽度为1μm，导通电流为0.25μA/μm，OFF电流为15fA /μm。 薄膜晶体管可以被施加到用作CMOS型SRAM的存储单元中的负载晶体管的p沟道MOS晶体管。