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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20120061767A1

    公开(公告)日：2012-03-15

    申请号：US13186163

    申请日：2011-07-19

    申请人： Yuichi HIRANO

    发明人： Yuichi HIRANO

    IPC分类号： H01L27/092 ,  H01L21/425

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/82385

    摘要： A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.

    摘要翻译： 半导体器件包括用于形成逻辑电路的核心晶体管和用于形成输入/输出电路的I / O晶体管。 从I / O型晶体管的n型杂质区NR的主表面到最下部的距离比从芯的n型杂质区NR的主表面到最下部的距离长 n型晶体管。 I / O p型晶体管的p型杂质区PR的主表面到最下部的距离比从芯p的p型杂质区的主表面到最下部的距离长 型晶体管。 从I / O型晶体管的n型杂质区域的主表面到最下部分的距离比从I / O的p型杂质区域的主表面到最下部分的长 p型晶体管。

    Semiconductor substrate and method of fabricating semiconductor device
    3.
    发明授权
    Semiconductor substrate and method of fabricating semiconductor device 失效
    半导体衬底及制造半导体器件的方法

    公开(公告)号：US06335267B1

    公开(公告)日：2002-01-01

    申请号：US09667498

    申请日：2000-09-22

    申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Takashi Ipposhi ,  Shigenobu Maeda ,  Yuichi Hirano

    发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Takashi Ipposhi ,  Shigenobu Maeda ,  Yuichi Hirano

    IPC分类号： H01L2120

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.

    摘要翻译： 提供半导体衬底和制造半导体器件的方法。 氧化膜（13）通过氧化SOI衬底（10）的边缘部分和下主表面而形成。 通过使用暴露在SOI衬底（10）的边缘部分和下部主表面上的氧化膜（11）作为下面的氧化膜，以类似于LOCOS（硅的局部氧化物）氧化的方式进行该氧化步骤。 然后，氧化膜（13）的厚度大于SOI衬底（10）的边缘部分和下主表面上的氧化物膜（11）的厚度。 半导体衬底防止在其边缘处产生灰尘颗粒。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20100314686A1

    公开(公告)日：2010-12-16

    申请号：US12861038

    申请日：2010-08-23

    申请人： Yuichi HIRANO

    发明人： Yuichi HIRANO

    IPC分类号： H01L27/12

    CPC分类号： H01L29/78615 ,  H01L21/76283 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

    摘要： A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

    摘要翻译： 栅电极被设置为使得其栅极宽度方向上的两端在平面视图中从有源区域突出。 部分沟槽隔离绝缘膜设置在对应于两端的下部的SOI衬底的表面中，并且在栅极宽度方向上的栅极电极的外侧的SOI衬底的表面中设置体接触区域， 与相应的部分沟槽隔离绝缘膜相邻。 体接触区域和体区域在部分沟槽隔离绝缘膜下通过SOI层（阱区）电连接。 此外，在栅极中心附近的源极区域的栅极宽度方向的表面设置有以较高浓度掺杂有P型杂质的源极连接区域。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20070241402A1

    公开(公告)日：2007-10-18

    申请号：US11733454

    申请日：2007-04-10

    申请人： Yuichi HIRANO

    发明人： Yuichi HIRANO

    IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

    CPC分类号： H01L29/78615 ,  H01L21/76283 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

    摘要： A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

    摘要翻译： 栅电极被设置为使得其栅极宽度方向上的两端在平面视图中从有源区域突出。 部分沟槽隔离绝缘膜设置在对应于两端的下部的SOI衬底的表面中，并且在栅极宽度方向上的栅极电极的外侧的SOI衬底的表面中设置体接触区域， 与相应的部分沟槽隔离绝缘膜相邻。 体接触区域和体区域在部分沟槽隔离绝缘膜下通过SOI层（阱区）电连接。 此外，在栅极中心附近的源极区域的栅极宽度方向的表面设置有以较高浓度掺杂有P型杂质的源极连接区域。

    Semiconductor device and method for producing the same
    7.
    发明授权
    Semiconductor device and method for producing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08513058B2

    公开(公告)日：2013-08-20

    申请号：US13019686

    申请日：2011-02-02

    申请人： Toshiaki Iwamatsu ,  Yuichi Hirano

    发明人： Toshiaki Iwamatsu ,  Yuichi Hirano

    IPC分类号： H01L25/00 ,  H01L23/52

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

    摘要： a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of the first layer.

    摘要翻译： 一种制造半导体器件的方法，其以层叠第一层和第二层的方式设置，以确保其TSV几乎为直线布置，包括：第一层制造步骤，包括制备基板，形成 在衬底的上表面上的输入/输出电路的晶体管，形成绝缘层以覆盖晶体管，并在绝缘层中形成TSV; 第二层制造步骤包括制备衬底的步骤，在衬底的上表面上形成逻辑电路的晶体管，形成绝缘层以覆盖晶体管，并在绝缘层中形成TSV; 将第一层和第二层的表面连接在与第一层和第二层的基板相对的一侧的连接步骤，以确保第一层的TSV和第二层的TSV几乎为直线 线; 以及去除第一层的基板的步骤。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07804132B2

    公开(公告)日：2010-09-28

    申请号：US11733454

    申请日：2007-04-10

    申请人： Yuichi Hirano

    发明人： Yuichi Hirano

    IPC分类号： H01L27/12

    CPC分类号： H01L29/78615 ,  H01L21/76283 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

    摘要： A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

    摘要翻译： 栅电极被设置为使得其栅极宽度方向上的两端从平面视图中的有源区域突出。 部分沟槽隔离绝缘膜设置在对应于两端的下部的SOI衬底的表面中，并且在栅极宽度方向上的栅极电极的外侧的SOI衬底的表面中设置体接触区域， 与相应的部分沟槽隔离绝缘膜相邻。 体接触区域和体区域在部分沟槽隔离绝缘膜下通过SOI层（阱区）电连接。 此外，在栅极中心附近的源极区域的栅极宽度方向的表面设置有以较高浓度掺杂有P型杂质的源极连接区域。

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20080179676A1

    公开(公告)日：2008-07-31

    申请号：US11971434

    申请日：2008-01-09

    申请人： Yuichi HIRANO ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yukio Maki ,  Mikio Tsujiuchi

    发明人： Yuichi HIRANO ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yukio Maki ,  Mikio Tsujiuchi

    IPC分类号： H01L27/12

    CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203

    摘要： While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain region of an access transistor), and the drain region of a load transistor, and the electrical coupling between the drain region of another driver transistor (which is also a source/drain region of another access transistor) and the drain region of another load transistor are established by wiring structures formed by using a SOI layer under an isolation oxide film which is partial trench isolation, respectively.

    摘要翻译： 在减小SRAM单元的形成面积的同时，抑制了各个晶体管的电特性的变化。 在SOI板中形成的SRAM单元中，驱动晶体管（其也是存取晶体管的源极/漏极区域）的漏极区域与负载晶体管的漏极区域之间的电耦合以及电耦合 另一个驱动晶体管的漏极区（也是另一个存取晶体管的源极/漏极区）和另一个负载晶体管的漏极区通过在隔离氧化膜下使用SOI层而形成的布线结构来建立，该SOI层是部分沟槽隔离 ， 分别。