公开(公告)号：US08064279B2

公开(公告)日：2011-11-22

申请号：US12502879

申请日：2009-07-14

申请人： Theodore W. Houston ,  Xiaowei Deng

发明人： Theodore W. Houston ,  Xiaowei Deng

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/12 ,  G11C2029/1202

摘要： An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method for screening SRAM bits in an SRAM array in which the wordline voltage is different than the array voltage during a portion of the screening test.

摘要翻译： 包含SRAM的集成电路，其提供开关以在屏蔽期间将SRAM字线电压与SRAM阵列电压分离，并且在SRAM位筛选测试的一部分期间还提供不同的字线和阵列电压。 一种用于在SRAM阵列中筛选SRAM位的方法，其中在屏蔽测试的一部分期间字线电压不同于阵列电压。

公开(公告)号：US20110043255A1

公开(公告)日：2011-02-24

申请号：US12916231

申请日：2010-10-29

申请人： Theodore W. Houston ,  Andrew Marshall

发明人： Theodore W. Houston ,  Andrew Marshall

IPC分类号： H03K5/22

CPC分类号： G05F3/205 ,  G05F3/30

摘要： The present invention provides a thermostatic biasing controller for use with an integrated circuit. In one embodiment, the thermostatic biasing controller includes a temperature sensing unit configured to determine an operating temperature of the integrated circuit. Additionally, the thermostatic biasing controller also includes a voltage controlling unit coupled to the temperature sensing unit and configured to provide a back-bias voltage corresponding to the operating temperature based on reducing a quiescent current of the integrated circuit.

摘要翻译： 本发明提供一种与集成电路一起使用的恒温偏压控制器。 在一个实施例中，恒温偏置控制器包括配置成确定集成电路的工作温度的温度感测单元。 此外，恒温偏压控制器还包括电压控制单元，其耦合到温度感测单元并且被配置为基于降低集成电路的静态电流来提供对应于工作温度的反偏压。

公开(公告)号：US20110020986A1

公开(公告)日：2011-01-27

申请号：US12840520

申请日：2010-07-21

申请人： Theodore W. Houston ,  Robert R. Garcia

发明人： Theodore W. Houston ,  Robert R. Garcia

IPC分类号： H01L21/8239

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104

摘要： An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent similar structures. A method of forming reduced area memory arrays by displacing adjacent similar structures along a common cell border. A method of building arrays using conventional array building software by forming unit pairs with cells that are not identical and are not mirror images or rotated versions of each other.

摘要翻译： 具有相邻类似结构的阵列的阵列，其在不垂直于小区边界的方向上跨越公共小区边界彼此移位，从而避免了相邻类似结构之间跨越小区边界设计规则违反。 通过沿着公共单元边界移位相邻的类似结构来形成缩小面积存储器阵列的方法。 使用常规阵列构建软件通过与不相同的单元形成单元对并且不是彼此的镜像或旋转版本来构建阵列的方法。

公开(公告)号：US20110019464A1

公开(公告)日：2011-01-27

申请号：US12507437

申请日：2009-07-22

申请人： Russell C. McMullan ,  Theodore W. Houston

发明人： Russell C. McMullan ,  Theodore W. Houston

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/412

摘要： An integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently. An integrated circuit containing an array of SRAM cells with PMOS drivers and passgates, and a p-well bias control circuit which biases p-wells in each SRAM column independently. A process of operating an integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently.

摘要翻译： 包含具有NMOS驱动器和通电闸门的SRAM单元阵列的集成电路，以及独立地偏置每个SRAM列中的n-阱的n阱偏置控制电路。 包含具有PMOS驱动器和通孔的SRAM单元阵列的集成电路，以及独立地偏置每个SRAM列中的p阱的p阱偏置控制电路。 操作包含具有NMOS驱动器和传动门的SRAM单元阵列的集成电路的工艺，以及独立地偏置每个SRAM列中的n-阱的n阱偏置控制电路。

公开(公告)号：US20100296337A1

公开(公告)日：2010-11-25

申请号：US12782908

申请日：2010-05-19

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/412

摘要： An integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The integrated circuit also contains circuitry so that auxiliary load transistors in addressed SRAM cells may be biased independently of half-addressed cells. A process of operating an integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The process includes biasing the auxiliary load transistors in addressed SRAM cells independently of half-addressed cells.

摘要翻译： 在每个数据节点上都有一个集成电路，其中包含具有辅助负载晶体管的SRAM单元。 集成电路还包含电路，使得寻址的SRAM单元中的辅助负载晶体管可以独立于半寻址单元被偏置。 在每个数据节点上操作包含具有辅助负载晶体管的SRAM单元的集成电路的处理。 该过程包括将寻址的SRAM单元中的辅助负载晶体管偏置于半寻址单元。

公开(公告)号：US07768820B2

公开(公告)日：2010-08-03

申请号：US11969589

申请日：2008-01-04

申请人： Theodore W. Houston ,  Howard L. Tigelaar

发明人： Theodore W. Houston ,  Howard L. Tigelaar

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104

摘要： Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the feedback structure is for use with an integrated circuit and includes a local interconnect configured to electrically connect an output of a CMOS inverter to another circuit in the integrated circuit. Additionally, the feedback structure also includes an interconnect extension to the local interconnect configured to proximately extend along a gate structure of the CMOS inverter to provide a reactive coupling between the output and the gate structure.

摘要翻译： 本公开的实施例提供反馈结构，构造反馈结构的方法和采用反馈结构的集成电路。 在一个实施例中，反馈结构用于集成电路，并且包括被配置为将CMOS反相器的输出电连接到集成电路中的另一电路的局部互连。 此外，反馈结构还包括局部互连的互连延伸，其被配置为沿着CMOS反相器的栅极结构近似延伸，以提供输出和栅极结构之间的电抗耦合。

公开(公告)号：US07755924B2

公开(公告)日：2010-07-13

申请号：US11969636

申请日：2008-01-04

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： G11C11/24

CPC分类号： G11C11/412 ,  Y10T29/49002

摘要： Embodiments of the present disclosure provide a memory element, a method of constructing a memory element, a method of operating a memory cell, an SRAM cell and an integrated circuit. In one embodiment, the memory element includes a pair of cross-connected CMOS inverters having first and second storage nodes. Additionally, the memory element also includes a capacitive component connected between the first and second storage nodes and configured to provide a supplemental capacitance to extend a read signal for sensing a memory state of the inverters.

摘要翻译： 本公开的实施例提供了存储元件，构造存储元件的方法，操作存储单元，SRAM单元和集成电路的方法。 在一个实施例中，存储器元件包括具有第一和第二存储节点的一对交叉连接的CMOS反相器。 此外，存储元件还包括连接在第一和第二存储节点之间并且被配置为提供补充电容以扩展用于感测逆变器的存储器状态的读取信号的电容元件。

公开(公告)号：US20090109785A1

公开(公告)日：2009-04-30

申请号：US11931098

申请日：2007-10-31

申请人： Theodore W. Houston ,  Andrew Marshall

发明人： Theodore W. Houston ,  Andrew Marshall

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C8/08 ,  G11C11/413

摘要： An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. A voltage differential generating circuit is operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein the differential is a function of the array supply voltage.

摘要翻译： 集成电路（IC）包括至少一个存储器阵列，其具有以多个行和列排列的多个存储器单元，该阵列还具有用于访问单元行的多个字线和用于访问列的列的多个位线 细胞。 电压差分发生电路可操作以提供相对于阵列电源电压的差分字线电压（VWL），其中差分是阵列电源电压的函数。

公开(公告)号：US07508698B2

公开(公告)日：2009-03-24

申请号：US11828476

申请日：2007-07-26

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C11/413

摘要： Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.

公开(公告)号：US07502247B2

公开(公告)日：2009-03-10

申请号：US11828465

申请日：2007-07-26

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C11/413

摘要： Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.

摘要翻译： 讨论了用于写入阵列的SRAM存储单元的方法和电路，其提供改进的静态噪声容限，并且在写入操作期间数据扰乱的风险最小。 写入方法首先将字线迅速提高到更低的读取电压电平，然后在允许所选行中的单元在相关位线上建立稳定的差分电压的时间延迟之后，将字线电压提升到升压或更高 写电压电平。 也可以与SRAM存储器阵列和写入方法相关联地使用SRAM位线增强电路，用于增强由常规SRAM单元阵列的相关联的第一和第二位线上的阵列的SRAM存储器单元产生的差分电压（例如， 常规6T差分电池）。 在一个实现中，SRAM位线增强电路包括半锁存器或连接到用于放大差分电压的阵列的相关位线对的读出放大器。