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公开(公告)号：US20110019464A1
公开(公告)日：2011-01-27
申请号：US12507437
申请日：2009-07-22
CPC分类号： G11C11/412
摘要： An integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently. An integrated circuit containing an array of SRAM cells with PMOS drivers and passgates, and a p-well bias control circuit which biases p-wells in each SRAM column independently. A process of operating an integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently.
摘要翻译： 包含具有NMOS驱动器和通电闸门的SRAM单元阵列的集成电路，以及独立地偏置每个SRAM列中的n-阱的n阱偏置控制电路。 包含具有PMOS驱动器和通孔的SRAM单元阵列的集成电路，以及独立地偏置每个SRAM列中的p阱的p阱偏置控制电路。 操作包含具有NMOS驱动器和传动门的SRAM单元阵列的集成电路的工艺，以及独立地偏置每个SRAM列中的n-阱的n阱偏置控制电路。
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公开(公告)号：US08379435B2
公开(公告)日：2013-02-19
申请号：US12507437
申请日：2009-07-22
CPC分类号： G11C11/412
摘要： An integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently. An integrated circuit containing an array of SRAM cells with PMOS drivers and passgates, and a p-well bias control circuit which biases p-wells in each SRAM column independently. A process of operating an integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently.
摘要翻译： 包含具有NMOS驱动器和通电闸门的SRAM单元阵列的集成电路，以及独立地偏置每个SRAM列中的n-阱的n阱偏置控制电路。 包含具有PMOS驱动器和通孔的SRAM单元阵列的集成电路，以及独立地偏置每个SRAM列中的p阱的p阱偏置控制电路。 操作包含具有NMOS驱动器和传动门的SRAM单元阵列的集成电路的工艺，以及独立地偏置每个SRAM列中的n-阱的n阱偏置控制电路。
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3.发明授权Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same 有权身体偏差协调器，协调身体偏压的方法和采用其的子电路电源公开(公告)号：US09124263B2
公开(公告)日：2015-09-01
申请号：US13116973
申请日：2011-05-26
IPC分类号： G05F1/10 , G05F3/02 , H03K19/00 , H03K17/687
CPC分类号： H03K19/0016 , H03K17/687 , H03K2217/0018 , H03K2217/0036
摘要： A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor.
摘要翻译： 身体偏置协调器被提供用于使用体区的晶体管。 在一个示例中，主体偏置协调器包括被配置为控制晶体管并使其可操作以在激活晶体管期间从源电压提供虚拟电源电压的控制单元。 身体偏置协调器还包括耦合到控制单元并被配置为在晶体管的激活期间将身体区域连接到虚拟电源电压的连接单元。 在替代实施例中，连接单元还被配置为在晶体管的非激活期间将身体区域连接到另一电压。
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公开(公告)号：US08891287B2
公开(公告)日：2014-11-18
申请号：US13196010
申请日：2011-08-02
IPC分类号： G11C11/40 , G11C11/412 , G11C11/419
CPC分类号： G11C11/412 , G11C11/419
摘要： A process of performing an SRAM single sided write operation including applying a positive bias increment to an isolated p-well containing a passgate in an addressed SRAM cell. A process of performing an SRAM single sided read operation including applying a negative bias increment to an isolated p-well containing a driver in an addressed SRAM cell. A process of performing an SRAM double sided write operation including applying a positive bias increment to an isolated p-well containing a passgate connected to a low data line in an addressed SRAM cell. A process of performing an SRAM double sided read operation including applying a negative bias increment to an isolated p-well containing a bit driver and applying a negative bias increment to an isolated p-well containing a bit-bar driver in an addressed SRAM cell.
摘要翻译： 一种执行SRAM单面写入操作的过程，包括在寻址的SRAM单元中对包含通孔的隔离p阱施加正偏置增量。 执行SRAM单面读取操作的过程包括对包含寻址的SRAM单元中的驱动器的隔离p阱施加负偏置增量。 执行SRAM双面写入操作的过程包括向包含连接到寻址的SRAM单元中的低数据线的通路的隔离p阱施加正偏置增量。 执行SRAM双面读取操作的过程包括向包含比特驱动器的隔离p阱施加负偏置增量，并且在寻址的SRAM单元中向包含位线驱动器的隔离p阱施加负偏置增量。
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公开(公告)号：US08535990B2
公开(公告)日：2013-09-17
申请号：US12975006
申请日：2010-12-21
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： H01L21/82
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/823807 , H01L21/823878 , H01L27/11 , H01L27/1207
摘要： An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation.
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公开(公告)号：US08379467B2
公开(公告)日：2013-02-19
申请号：US13043229
申请日：2011-03-08
申请人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
发明人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/413 , G11C11/419 , G11C29/12005 , G11C29/50 , G11C2029/5002
摘要： Integrated circuit for performing test operation of static RAM bit and for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, the integrated circuit has a built-in self-test circuit for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design.
摘要翻译： 集成电路，用于执行静态RAM位的测试操作，并用于测量SRAM位的读取余量，写入余量和稳定裕度，其中包含SRAM阵列架构和电路设计的操作电路。 此外，集成电路还具有内置的自检电路，用于测量SRAM的读取余量，写入余量和稳定裕度，排除了SRAM阵列结构和电路设计的影响。
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公开(公告)号：US20120300537A1
公开(公告)日：2012-11-29
申请号：US13301217
申请日：2011-11-21
CPC分类号： H01L27/1116 , H01L21/76895 , H01L27/0207 , H01L27/1104
摘要： An integrated circuit containing an SRAM array having a strap row. The strap row has a substrate contact structure that includes a substrate contact plug and a tap layer.
摘要翻译： 包含具有带排的SRAM阵列的集成电路。 带排具有包括衬底接触插塞和抽头层的衬底接触结构。
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公开(公告)号：US20120300536A1
公开(公告)日：2012-11-29
申请号：US13301132
申请日：2011-11-21
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： G11C11/34
CPC分类号： G11C11/412 , G11C5/025 , G11C5/063 , H01L21/76895 , H01L27/0207 , H01L27/1104
摘要： An integrated circuit containing an SRAM array having a strap row and an SRAM cell row. The strap row includes a tap connecting region that connects two columnar regions of a first polarity well. The strap row also includes a well tap active area in a tap connecting well region. The well tap active area includes a tap layer and a well contact plug that is disposed on the top surface of the tap layer.
摘要翻译： 包含具有带行和SRAM单元行的SRAM阵列的集成电路。 带排包括连接第一极性的两个柱状区域的抽头连接区域。 带排还包括在水龙头连接井区域中的井口活动区域。 阱分接器活动区域包括配置在抽头层顶表面上的抽头层和阱接触插塞。
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公开(公告)号：US08310860B1
公开(公告)日：2012-11-13
申请号：US13301287
申请日：2011-11-21
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/1104 , H01L27/1116
摘要： An integrated circuit containing an SRAM array having a strap row. The strap row has a well tap active area that partially overlaps adjacent first polarity wells and a second polarity well that is located between the adjacent first polarity wells. A well contact plug is disposed on a top surface of a tap layer located within the well tap active area.
摘要翻译： 包含具有带排的SRAM阵列的集成电路。 带排具有与相邻的第一极性阱部分重叠的阱分接有源区域和位于相邻的第一极性阱之间的第二极性阱。 阱接触插头设置在位于阱分接头活动区域内的抽头层的顶表面上。
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公开(公告)号：US20120264293A1
公开(公告)日：2012-10-18
申请号：US13530368
申请日：2012-06-22
IPC分类号： H01L21/768
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11 , Y10S257/903
摘要： An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.
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