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公开(公告)号：US5890196A
公开(公告)日：1999-03-30
申请号：US623499
申请日：1996-03-28
CPC分类号： G06F13/1663
摘要： An external bus master (205) accesses a DRAM (207) using a memory controller (804) internal to a data processor (3) without the use of external multiplexers or any other external circuitry. The need for external multiplexers and even a dedicated integrated circuit pin for providing external control during external master initiated DRAM accesses is removed by the implementation of a circuit and technique for multiplexing row and column addresses of the DRAM internally within the data processor.
摘要翻译： 外部总线主机（205）使用数据处理器（3）内部的存储器控制器（804）访问DRAM（207），而不使用外部多路复用器或任何其它外部电路。 通过实现用于在数据处理器内部复用DRAM的行和列地址的电路和技术来消除对在外部主发起的DRAM访问期间提供外部控制的外部多路复用器甚至专用集成电路引脚的需求。
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公开(公告)号：US5524215A
公开(公告)日：1996-06-04
申请号：US133413
申请日：1993-10-05
申请人： James G. Gay
发明人： James G. Gay
IPC分类号： G06F13/36 , G06F13/364 , G06F13/42
CPC分类号： G06F13/4213 , G06F13/364
摘要： A bus protocol uses signals to designate a bus transfer termination (BTT*) and a bus grant relinquish (BGR*). The BTT* signal is an output which is asserted by a bus master which currently has ownership of a bus to indicate to other potential bus masters that a bus transfer is complete and that bus ownership may be transferred to another bus master. The BGR* signal is an input to a bus master. When BGR* is asserted, a bus arbiter/controller is informing the current bus master that the bus must be relinquished as soon as possible, after the deassertion of the Bus Grant signal, with no regard for locked sequences. If BGR* is deasserted, the bus arbiter is informing the current bus master that the bus can be relinquished at a time which is convenient for the current bus master. In general, BGR* is a bit which indicates the urgency of a pending bus ownership transfer.
摘要翻译： 总线协议使用信号来指定总线传输终止（BTT *）和总线授权放弃（BGR *）。 BTT *信号是由总线主机断言的输出，该总线主机当前拥有总线的所有权，以向其他潜在总线主机指示总线传输完成，并且总线所有权可以传输到另一个总线主机。 BGR *信号是总线主机的输入。 当BGR *被断言时，总线仲裁器/控制器通知当前总线主机，在总线授权信号解除之后，尽快放弃总线，而不考虑锁定的序列。 如果BGR *被置为无效，则总线仲裁器通知当前总线主控器，总线可以在当前总线主机方便的时间放弃。 一般来说，BGR *有一点表示正在进行的公交车所有权转让的紧急性。
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23.发明授权Output circuit for interfacing integrated circuits having different power supply potentials 失效用于接口具有不同电源电位的集成电路的输出电路
公开(公告)号：US5396128A
公开(公告)日：1995-03-07
申请号：US120506
申请日：1993-09-13
IPC分类号： H01L21/8234 , H01L27/06 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0948
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： An output driver circuit has a circuitry portion (70) which is used to generate a Drive-Hi control signal in response to an Output Enable, an optional Precondition signal, and a Data Input signal. A circuit portion (75) ensures that the Drive-Hi control signal is maintained at a voltage which is substantially equal to Vdd when the Output Enable is deactivated. Circuit portion (80) selectively controls the Data Output by driving Vdd onto the Data Output in response to the Drive-Hi control signal being activated. A circuit portion (100) functions to selectively drive the Data Output to a logic zero (ground potential) when a Drive-Lo signal is asserted. Circuit portions (90 and 95) generate the Drive-Lo signal in response to the Output Enable, the optional Precondition signal, and the Data Input signal. In general, the output driver circuit allows an integrated circuit powered at a first voltage to interface to another integrated circuit which is powered at a higher second voltage without loss of performance, without excessive leakage currents, without crossover current, and without increasing gate oxide stresses.
摘要翻译： 输出驱动器电路具有电路部分（70），其用于响应于输出使能，可选的预条件信号和数据输入信号来产生Drive-Hi控制信号。 当禁用输出使能时，电路部分（75）确保Drive-Hi控制信号保持在基本上等于Vdd的电压。 电路部分（80）响应于驱动Hi控制信号被激活，通过将Vdd驱动到数据输出端来选择性地控制数据输出。 当Drive-Lo信号被断言时，电路部分（100）用于选择性地将数据输出驱动到逻辑零（地电位）。 电路部分（90和95）响应于输出使能，可选前置条件信号和数据输入信号产生Drive-Lo信号。 通常，输出驱动器电路允许以第一电压供电的集成电路与另一个集成电路接口，该另一个集成电路在较高的第二电压下供电而不损失性能，而没有过多的漏电流，而不会增加栅极氧化应力 。
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