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1.发明授权Method and apparatus for accessing a chip-selectable device in a data processing system 失效用于在数据处理系统中访问芯片可选设备的方法和装置
公开(公告)号：US5740382A
公开(公告)日：1998-04-14
申请号：US623482
申请日：1996-03-28
CPC分类号： G06F13/1694
摘要： A user may program a data processor (3) such that external master chip select accesses can be either the same or different length of time than an internal master access through the use of a control register (810). Additionally, the user can turn off the internal transfer acknowledge logic and add external transfer acknowledge logic while still using the internal chip select and write enable generation logic (8) of the data processor. This feature is user programmable on a chip select basis and provides a flexible solution which allows the user to compensate for different external master accesses without requiring external chip select and write enable logic. Therefore, overhead is conserved and efficiency is increased.
摘要翻译： 用户可以对数据处理器（3）进行编程，使得通过使用控制寄存器（810），外部主芯片选择访问可以与内部主机访问相同或不同的时间长度。 此外，用户可以在仍然使用数据处理器的内部芯片选择和写入使能生成逻辑（8）的同时关闭内部传输确认逻辑并添加外部传输确认逻辑。 该功能是用户可编程的芯片选择基础，并提供灵活的解决方案，允许用户补偿不同的外部主访问，而不需要外部芯片选择和写使能逻辑。 因此，节省开销，提高效率。
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公开(公告)号：US5890196A
公开(公告)日：1999-03-30
申请号：US623499
申请日：1996-03-28
CPC分类号： G06F13/1663
摘要： An external bus master (205) accesses a DRAM (207) using a memory controller (804) internal to a data processor (3) without the use of external multiplexers or any other external circuitry. The need for external multiplexers and even a dedicated integrated circuit pin for providing external control during external master initiated DRAM accesses is removed by the implementation of a circuit and technique for multiplexing row and column addresses of the DRAM internally within the data processor.
摘要翻译： 外部总线主机（205）使用数据处理器（3）内部的存储器控制器（804）访问DRAM（207），而不使用外部多路复用器或任何其它外部电路。 通过实现用于在数据处理器内部复用DRAM的行和列地址的电路和技术来消除对在外部主发起的DRAM访问期间提供外部控制的外部多路复用器甚至专用集成电路引脚的需求。
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公开(公告)号：US5799160A
公开(公告)日：1998-08-25
申请号：US669071
申请日：1996-06-24
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： Control over bus arbitration within a data processing system between a plurality of bus devices (101, 102) coupled by a bus (103) is performed in a user programmable manner by implementing logic circuitry that is responsive to a user programmable bit within a register (203) so that when the bit is asserted, the bus device (102) is able to maintain control over access to the external bus (103). Such a technique is useful for permitting a processor (201) to maintain mastership of an external bus (103) with respect to a direct memory access device (101) also coupled to the bus (103).
摘要翻译： 在由总线（103）耦合的多个总线设备（101,102）之间的数据处理系统内的总线仲裁的控制以用户可编程的方式通过实现响应于寄存器内的用户可编程位的逻辑电路 203），使得当该位被置位时，总线装置（102）能够保持对对外部总线（103）的访问的控制。 这种技术对于允许处理器（201）相对于也耦合到总线（103）的直接存储器访问设备（101）来维持外部总线（103）的掌握是有用的。
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公开(公告)号：US5872940A
公开(公告)日：1999-02-16
申请号：US627669
申请日：1996-04-01
CPC分类号： G06F13/1694
摘要： A system bus controller (103) within a processor (101) includes programmable logic for different modes of chip enable signals on a per-address-space basis. This allows for a "glueless" interface (107) between the processor (101) and different types of external devices (111, 112, 113), such as memory devices. A chip select register value 604, 608, 612 is preprogrammed with respect to each external device coupled to the processor (101). This preprogrammed register value 604, 608, 612 is used by the system bus controller (103) to uniquely configure a read/write access signal to be sent to each of the external devices (111, 112, 113).
摘要翻译： 处理器（101）内的系统总线控制器（103）包括用于每个地址空间的不同模式的芯片使能信号的可编程逻辑。 这允许在处理器（101）和不同类型的外部设备（111,112,113）之间的诸如存储器设备之间的“无胶粘”接口（107）。 相对于耦合到处理器（101）的每个外部设备，对芯片选择寄存器值604,608,612进行预编程。 系统总线控制器（103）使用该预编程寄存器值604,608,612来唯一地配置要发送到每个外部设备（111,112,113）的读/写访问信号。
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5.发明授权Method and apparatus for entering a low-power mode and controlling an external bus of a data processing system during low-power mode 失效用于在低功率模式下进入低功率模式和控制数据处理系统的外部总线的方法和装置
公开(公告)号：US5471625A
公开(公告)日：1995-11-28
申请号：US125851
申请日：1993-09-27
CPC分类号： G06F1/3203
摘要： A method and apparatus for placing a data processor (12) into a low-power mode of operation using a system (10). The system (10) has a processor (12). The processor (12) has access to a bus (18). The bus (18) is coupled to a bus controller (14). The processor (12) sends a broadcast cycle out through the bus (18) when the processor (12) desires to enter a low-power mode of operation. The bus controller (14) determines that the broadcast cycle has been sent on the bus (18). The bus controller (14) waits a predetermined amount of time to process the low-power request and grants permission to the processor (12) to enter the low-power mode via the communication of a transmission termination signal. The processor (12) conditionally drives either logic ones or a tri-state value onto the bus (18) depending upon whether or not the processor (12) has been granted ownership of the bus (18).
摘要翻译： 一种用于使用系统（10）将数据处理器（12）置于低功率操作模式的方法和装置。 系统（10）具有处理器（12）。 处理器（12）可访问总线（18）。 总线（18）耦合到总线控制器（14）。 当处理器（12）希望进入低功率操作模式时，处理器（12）通过总线（18）发送广播周期。 总线控制器（14）确定广播周期已经在总线（18）上发送。 总线控制器（14）等待预定量的时间来处理低功率请求，并通过传输终止信号的通信向处理器（12）授予许可以进入低功率模式。 处理器（12）根据处理器（12）是否被授予总线（18）的所有权，有条件地将逻辑1或三态值驱动到总线（18）上。
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6.发明授权Circuit for controlling data communication with synchronous storage circuitry and method of operation 有权用于控制与同步存储电路的数据通信的电路和操作方法公开(公告)号：US07859299B1
公开(公告)日：2010-12-28
申请号：US12500975
申请日：2009-07-10
申请人： James G. Gay , Carlos A. Greaves
发明人： James G. Gay , Carlos A. Greaves
CPC分类号： G11C7/1078 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1093
摘要： A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp circuit is disabled. After disabling the clamp circuit, while the termination circuit remains enabled, both a first differential comparator and a second differential comparator are enabled. The first differential comparator receives a first differential input signal at a first input and a second differential input signal at a second input. The second differential comparator detects when a difference between the first differential input signal and the second differential input signal is greater than a predetermined value and enables transfer of an output of the first differential comparator to a memory controller.
摘要翻译： 方法和电路包括提供用于接收输入信号的至少一个导体。 终端电路和钳位电路耦合到至少一个导体。 当钳位电路保持使能时，使能端接电路。 钳位电路被禁止。 禁用钳位电路后，当终端电路保持使能时，第一个差分比较器和第二个差分比较器都使能。 第一差分比较器在第一输入端接收第一差分输入信号，在第二输入端接收第二差分输入信号。 第二差分比较器检测第一差分输入信号和第二差分输入信号之间的差是否大于预定值，并且能够将第一差分比较器的输出传送到存储器控制器。
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7.发明授权
公开(公告)号：US5162672A
公开(公告)日：1992-11-10
申请号：US632901
申请日：1990-12-24
申请人： Steven C. McMahan , Kenneth C. Scheuer , William B. Ledbetter, Jr. , Michael G. Gallup , James G. Gay
发明人： Steven C. McMahan , Kenneth C. Scheuer , William B. Ledbetter, Jr. , Michael G. Gallup , James G. Gay
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/017581 , H03K19/0005
摘要： A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance then the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.
摘要翻译： 数据处理器具有至少一个输出端，数据处理器的用户可以根据数据处理器的应用环境来改变其输出阻抗。 输出缓冲级的第一输出缓冲器具有预定的输出阻抗，并且耦合在级的输入端和输出端子之间。 第一输出缓冲器提供第一输出端阻抗。 具有较低输出阻抗的第二输出缓冲器然后与第一输出缓冲器可以被选择性地耦合到第一输出缓冲器以减小输出端子的输出阻抗。 输出缓冲器的耦合由数据处理器的用户控制，数据处理器的用户提供用于选择多个预定输出端子阻抗值之一的控制输入。
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8.发明授权Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation 失效数据处理器集成电路，具有可选择的复用/非复用地址和数据操作模式
公开(公告)号：US5086407A
公开(公告)日：1992-02-04
申请号：US361539
申请日：1989-06-05
申请人： Ralph C. McGarity , William B. Ledbetter, Jr. , Steven C. McMahan , Michael G. Gallup , Russell Stanphill , James G. Gay
发明人： Ralph C. McGarity , William B. Ledbetter, Jr. , Steven C. McMahan , Michael G. Gallup , Russell Stanphill , James G. Gay
CPC分类号： G06F13/4208 , G06F15/7832
摘要： A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division multiplexed with data bits when both are written to external circuitry. In a second or normal mode, the circuit's address and data terminals are not connected and address bits are communicated with the circuit independent of data bits which are communicated with the circuit. No circuitry external to the integrated circuit is required to implement the multiplexed mode. A control portion insures that bit collisions are avoided when the circuit is in the multiplexed mode.
摘要翻译： 具有可被编程为将电路的地址和数据总线端子置于两种模式之一的输入的单芯片数据处理器集成电路。 在第一或多路复用模式下，电路的地址和数据终端直接连接，并且当两者都写入外部电路时，地址位与数据位进行时分复用。 在第二或正常模式下，电路的地址和数据端子不连接，地址位与电路无关地与电路通信的数据位通信。 需要集成电路外部的电路来实现复用模式。 控制部分确保当电路处于复用模式时避免位冲突。
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公开(公告)号：US5029072A
公开(公告)日：1991-07-02
申请号：US144638
申请日：1988-01-11
CPC分类号： G06F12/1027 , G06F12/126
摘要： In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed using translation tables in the memory. The PMMU maintains a set of recently used translators in a translator cache. In response to a particular lock value contained in the translation tables in association with the translation descriptor for a particular page, the PMMU sets a lock indicator in the translator cache associated with the corresponding translator, to preclude replacement of this translator in the translator cache. A lock warning mechanism provides a lock warning signal whenever all but a predetermined number of the translators in the cache are locked. In response, the PMMU can warn the processor that the translator cache is in danger of becoming full of locked translators. Preferably, the PMMU is also inhibited from locking the last translator in the cache.
摘要翻译： 在数据处理系统中，分页存储器管理单元（PMMU）使用由存储器中的翻译表构造的翻译器将处理器提供的逻辑地址转换为存储器中的物理地址。 PMMU在翻译缓存中维护一组最近使用的翻译器。 响应于与特定页面的翻译描述符相关联的转换表中包含的特定锁定值，PMMU在与对应的翻译器相关联的翻译器缓存中设置锁定指示符，以排除在翻译器高速缓存中替换该翻译器。 只要高速缓存中的预定数量的转换器都被锁定，锁定警告机制就会提供锁定警告信号。 作为响应，PMMU可以警告处理器翻译器缓存有变得充满锁定的翻译器的危险。 优选地，PMMU也被禁止锁定高速缓存中的最后一个转换器。
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10.发明申请CIRCUIT FOR CONTROLLING DATA COMMUNICATION WITH SYNCHRONOUS STORAGE CIRCUITRY AND METHOD OF OPERATION 有权用于同步存储电路控制数据通信的电路和操作方法公开(公告)号：US20110006804A1
公开(公告)日：2011-01-13
申请号：US12500975
申请日：2009-07-10
申请人： James G. Gay , Carlos A. Greaves
发明人： James G. Gay , Carlos A. Greaves
IPC分类号： H03K17/16
CPC分类号： G11C7/1078 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1093
摘要： A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp circuit is disabled. After disabling the clamp circuit, while the termination circuit remains enabled, both a first differential comparator and a second differential comparator are enabled. The first differential comparator receives a first differential input signal at a first input and a second differential input signal at a second input. The second differential comparator detects when a difference between the first differential input signal and the second differential input signal is greater than a predetermined value and enables transfer of an output of the first differential comparator to a memory controller.
摘要翻译： 方法和电路包括提供用于接收输入信号的至少一个导体。 终端电路和钳位电路耦合到至少一个导体。 当钳位电路保持使能时，使能端接电路。 钳位电路被禁止。 禁用钳位电路后，当终端电路保持使能时，第一个差分比较器和第二个差分比较器都使能。 第一差分比较器在第一输入端接收第一差分输入信号，在第二输入端接收第二差分输入信号。 第二差分比较器检测第一差分输入信号和第二差分输入信号之间的差是否大于预定值，并且能够将第一差分比较器的输出传送到存储器控制器。
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