公开(公告)号：US09111607B2

公开(公告)日：2015-08-18

申请号：US13907484

申请日：2013-05-31

申请人： James G. Gay

发明人： James G. Gay

IPC分类号： G11C7/22 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10

CPC分类号： G11C7/222 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1066

摘要： A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees.

公开(公告)号：US5890196A

公开(公告)日：1999-03-30

申请号：US623499

申请日：1996-03-28

申请人： Michael R. Miller ,  Nancy G. Woodbridge ,  Thomas A. Volpe ,  James G. Gay

发明人： Michael R. Miller ,  Nancy G. Woodbridge ,  Thomas A. Volpe ,  James G. Gay

IPC分类号： G06F13/16 ,  G06F12/00

CPC分类号： G06F13/1663

摘要： An external bus master (205) accesses a DRAM (207) using a memory controller (804) internal to a data processor (3) without the use of external multiplexers or any other external circuitry. The need for external multiplexers and even a dedicated integrated circuit pin for providing external control during external master initiated DRAM accesses is removed by the implementation of a circuit and technique for multiplexing row and column addresses of the DRAM internally within the data processor.

摘要翻译： 外部总线主机（205）使用数据处理器（3）内部的存储器控​​制器（804）访问DRAM（207），而不使用外部多路复用器或任何其它外部电路。 通过实现用于在数据处理器内部复用DRAM的行和列地址的电路和技术来消除对在外部主发起的DRAM访问期间提供外部控制的外部多路复用器甚至专用集成电路引脚的需求。

公开(公告)号：US5524215A

公开(公告)日：1996-06-04

申请号：US133413

申请日：1993-10-05

申请人： James G. Gay

发明人： James G. Gay

IPC分类号： G06F13/36 ,  G06F13/364 ,  G06F13/42

CPC分类号： G06F13/4213 ,  G06F13/364

摘要： A bus protocol uses signals to designate a bus transfer termination (BTT*) and a bus grant relinquish (BGR*). The BTT* signal is an output which is asserted by a bus master which currently has ownership of a bus to indicate to other potential bus masters that a bus transfer is complete and that bus ownership may be transferred to another bus master. The BGR* signal is an input to a bus master. When BGR* is asserted, a bus arbiter/controller is informing the current bus master that the bus must be relinquished as soon as possible, after the deassertion of the Bus Grant signal, with no regard for locked sequences. If BGR* is deasserted, the bus arbiter is informing the current bus master that the bus can be relinquished at a time which is convenient for the current bus master. In general, BGR* is a bit which indicates the urgency of a pending bus ownership transfer.

摘要翻译： 总线协议使用信号来指定总线传输终止（BTT *）和总线授权放弃（BGR *）。 BTT *信号是由总线主机断言的输出，该总线主机当前拥有总线的所有权，以向其他潜在总线主机指示总线传输完成，并且总线所有权可以传输到另一个总线主机。 BGR *信号是总线主机的输入。 当BGR *被断言时，总线仲裁器/控制器通知当前总线主机，在总线授权信号解除之后，尽快放弃总线，而不考虑锁定的序列。 如果BGR *被置为无效，则总线仲裁器通知当前总线主控器，总线可以在当前总线主机方便的时间放弃。 一般来说，BGR *有一点表示正在进行的公交车所有权转让的紧急性。

公开(公告)号：US5485602A

公开(公告)日：1996-01-16

申请号：US172985

申请日：1993-12-27

申请人： William B. Ledbetter, Jr. ,  Daniel M. McCarthy ,  James G. Gay

发明人： William B. Ledbetter, Jr. ,  Daniel M. McCarthy ,  James G. Gay

IPC分类号： G06F1/12 ,  G06F13/42 ,  G06F1/04

CPC分类号： G06F13/4217

摘要： A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs operations in response to the CLK signal. The bus is allowed to operate at a frequency which is less than or equal to the operational frequency of the CLK. The bus clock is typically either equal to the clock in frequency or runs at one-half or one-quarter speed. A CLKEN* signal input to the processor (10) is asserted to indicate an active edge of the external bus clock and synchronize the active edge of the external bus clock with an active edge of CLK to allow an active edge of CLK to perform bus operations which coincide with the active edge of the external bus clock. In another form, an internal counter/control circuit (20) may be used internal to the processor (10) to generate internal CLKEN* signals.

摘要翻译： 数据处理系统接收用于执行数据处理器（10）内部的操作的CLK信号。 数据处理器（10）具有响应于CLK信号执行操作的CPU（12）。 允许总线以小于或等于CLK工作频率的频率工作。 总线时钟通常等于时钟频率或以一半或四分之一速度运行。 输入到处理器（10）的CLKEN *信号被断言以指示外部总线时钟的有效边沿，并且将外部总线时钟的有效边沿与CLK的有效边沿同步，以允许CLK的有效沿执行总线操作 这与外部总线时钟的有效边沿一致。 在另一种形式中，内部计数器/控制电路（20）可以在处理器（10）内部使用，以产生内部CLKEN *信号。

公开(公告)号：US5396128A

公开(公告)日：1995-03-07

申请号：US120506

申请日：1993-09-13

申请人： James E. Dunning ,  James R. Lundberg ,  Richard S. Ramus ,  James G. Gay

发明人： James E. Dunning ,  James R. Lundberg ,  Richard S. Ramus ,  James G. Gay

IPC分类号： H01L21/8234 ,  H01L27/06 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0948

CPC分类号： H03K19/00315 ,  H03K2217/0018

摘要： An output driver circuit has a circuitry portion (70) which is used to generate a Drive-Hi control signal in response to an Output Enable, an optional Precondition signal, and a Data Input signal. A circuit portion (75) ensures that the Drive-Hi control signal is maintained at a voltage which is substantially equal to Vdd when the Output Enable is deactivated. Circuit portion (80) selectively controls the Data Output by driving Vdd onto the Data Output in response to the Drive-Hi control signal being activated. A circuit portion (100) functions to selectively drive the Data Output to a logic zero (ground potential) when a Drive-Lo signal is asserted. Circuit portions (90 and 95) generate the Drive-Lo signal in response to the Output Enable, the optional Precondition signal, and the Data Input signal. In general, the output driver circuit allows an integrated circuit powered at a first voltage to interface to another integrated circuit which is powered at a higher second voltage without loss of performance, without excessive leakage currents, without crossover current, and without increasing gate oxide stresses.

摘要翻译： 输出驱动器电路具有电路部分（70），其用于响应于输出使能，可选的预条件信号和数据输入信号来产生Drive-Hi控制信号。 当禁用输出使能时，电路部分（75）确保Drive-Hi控制信号保持在基本上等于Vdd的电压。 电路部分（80）响应于驱动Hi控制信号被激活，通过将Vdd驱动到数据输出端来选择性地控制数据输出。 当Drive-Lo信号被断言时，电路部分（100）用于选择性地将数据输出驱动到逻辑零（地电位）。 电路部分（90和95）响应于输出使能，可选前置条件信号和数据输入信号产生Drive-Lo信号。 通常，输出驱动器电路允许以第一电压供电的集成电路与另一个集成电路接口，该另一个集成电路在较高的第二电压下供电而不损失性能，而没有过多的漏电流，而不会增加栅极氧化应力 。

公开(公告)号：US5127089A

公开(公告)日：1992-06-30

申请号：US374906

申请日：1989-07-03

申请人： James G. Gay ,  William B. Ledbetter, Jr.

发明人： James G. Gay ,  William B. Ledbetter, Jr.

IPC分类号： G06F13/364 ,  G06F15/17

CPC分类号： G06F13/364 ,  G06F15/17

摘要： A data processing system having a mechanism for changing communication bus mastership when a series of locked operand transfer sequences are executed. The system has at least two processors coupled via the communication bus and a bus arbiter. In one form, a locked transfer end signal is provided by each processor to the bus arbiter so that if a high priority need is recognized by the bus arbiter during early execution of a plurality of locked operand transfer sequences the high priority need can be responded to by the bus arbiter before completion of all of the locked sequences. In another form, control signals are provided by the bus arbiter to each processor to accomplish the equivalent function.

摘要翻译： 一种数据处理系统，具有当执行一系列锁定操作数传送序列时改变通信总线主管性的机制。 该系统具有经由通信总线和总线仲裁器耦合的至少两个处理器。 在一种形式中，锁定的传送结束信号由每个处理器提供给总线仲裁器，使得如果在多个锁定的操作数传送序列的早期执行期间由总线仲裁器识别到高优先级的需要，则可以对高优先级的需求作出响应 由总线仲裁器完成所有的锁定序列。 在另一种形式中，控制信号由总线仲裁器提供给每个处理器以实现等效功能。

公开(公告)号：US5799160A

公开(公告)日：1998-08-25

申请号：US669071

申请日：1996-06-24

申请人： Nancy G. Woodbridge ,  Thomas A. Volpe ,  James G. Gay

发明人： Nancy G. Woodbridge ,  Thomas A. Volpe ,  James G. Gay

IPC分类号： G06F13/364 ,  G06F13/00

CPC分类号： G06F13/364

摘要： Control over bus arbitration within a data processing system between a plurality of bus devices (101, 102) coupled by a bus (103) is performed in a user programmable manner by implementing logic circuitry that is responsive to a user programmable bit within a register (203) so that when the bit is asserted, the bus device (102) is able to maintain control over access to the external bus (103). Such a technique is useful for permitting a processor (201) to maintain mastership of an external bus (103) with respect to a direct memory access device (101) also coupled to the bus (103).

摘要翻译： 在由总线（103）耦合的多个总线设备（101,102）之间的数据处理系统内的总线仲裁的控制以用户可编程的方式通过实现响应于寄存器内的用户可编程位的逻辑电路 203），使得当该位被置位时，总线装置（102）能够保持对对外部总线（103）的访问的控制。 这种技术对于允许处理器（201）相对于也耦合到总线（103）的直接存储器访问设备（101）来维持外部总线（103）的掌握是有用的。

公开(公告)号：US5638528A

公开(公告)日：1997-06-10

申请号：US143731

申请日：1993-11-01

申请人： James G. Gay ,  Ronald W. Stence ,  Jefferson L. Gokingco ,  John P. Hansen

发明人： James G. Gay ,  Ronald W. Stence ,  Jefferson L. Gokingco ,  John P. Hansen

IPC分类号： G06F13/16 ,  G06F12/02 ,  G06F12/08 ,  G06F13/42

CPC分类号： G06F13/4217

摘要： A method and apparatus for controlling a bus within a data processing system has a first control bit (SAS*), and second control bit (CLA*), and at least one termination signal (TA*, TRA*, TEA*). The CLA* signal is an input to a primary master (10). The primary master (10) provides a base address external to the primary master (10) so that a slave device can access the base address. The CLA* signal is asserted by the slave device to signal that the base address is to be cycled in a bit-wise circular fashion to provide a plurality of addresses out from the primary master (10) wherein each address in the plurality is derived from the base address internal to the primary master (10). Typically four addresses are provided per base address via the internal control of the primary master (10) in response to three sequential assertions of the CLA* signal.

摘要翻译： 用于在数据处理系统内控制总线的方法和装置具有第一控制位（SAS *）和第二控制位（CLA *）和至少一个终止信号（TA *，TRA *，TEA *）。 CLA *信号是对主主机（10）的输入。 主主机（10）提供主主机（10）外部的基地址，使得从设备可以访问基地址。 CLA *信号由从设备确定，以指示基地址将以逐位循环方式循环，以从主主机（10）提供多个地址，其中多个地址中的每个地址来自 主站（10）内部的基地址。 通常，响应于CLA​​ *信号的三个连续断言，通过主主机（10）的内部控制，每个基地址提供四个地址。

公开(公告)号：US5617531A

公开(公告)日：1997-04-01

申请号：US500271

申请日：1995-07-10

申请人： Alfred L. Crouch ,  Matthew D. Pressly ,  James G. Gay ,  Clark G. Shepard ,  Pamela S. Laakso

发明人： Alfred L. Crouch ,  Matthew D. Pressly ,  James G. Gay ,  Clark G. Shepard ,  Pamela S. Laakso

IPC分类号： G11C29/00 ,  G11C29/44 ,  G06F11/08

CPC分类号： G11C29/44 ,  G11C29/006 ,  G11C2029/1206

摘要： A data processor (10) has a single test controller (11). The test controller (11) has a test pattern generator portion (26) and a memory verification element (27). The test pattern generator (26) generates and communicates a plurality of test patterns to the plurality of memories (12, 13, and 14) through a second storage device (17). A first storage device (16) is used to store data read from the plurality of memories (12, 13, and 14). The data from the first storage device is selectively accessed by the memory verification element (27) via the bus (31). A bit (32) or more than one bit is used to communicate to external to the processor (10) whether the memories (12, 13, and 14) are operating in an error free manner.

摘要翻译： 数据处理器（10）具有单个测试控制器（11）。 测试控制器（11）具有测试图形发生器部分（26）和存储器验证元件（27）。 测试图案生成器（26）通过第二存储装置（17）产生并传送多个测试图案到多个存储器（12,13和14）。 第一存储装置（16）用于存储从多个存储器（12,13和14）读取的数据。 来自第一存储设备的数据经由总线（31）由存储器验证元件（27）选择性地访问。 位（32）或多于一位的位用于与处理器（10）的外部通信，无论存储器（12,13和14）是否以无错误的方式操作。

公开(公告)号：US5579492A

公开(公告)日：1996-11-26

申请号：US143667

申请日：1993-11-01

申请人： James G. Gay

发明人： James G. Gay

IPC分类号： G06F13/364 ,  G06F13/22

CPC分类号： G06F13/364

摘要： A method and apparatus for controlling a bus within a data processing system has a first control bit (SAS*), a second control bit (CLA*), and at least one termination signal (TA*, TRA*, TEA*). The termination signals cannot usually be provided as a valid signal for every clock edge of the apparatus when the apparatus is operating at a high frequency. Therefore, within in the apparatus, the termination signals are not always sampled at every clock edge. Instead, there is at least one counter within the primary master (10) which delays the sampling of the termination bits for a predetermined number of clocks cycles to allow time for the termination signals to settle and become valid logic signals before sampling begins. The SAS* signal communicates, external to the primary master (10), whether the sampling of the termination bits is being performed, or the sampling of the termination bits is being suppressed.

摘要翻译： 用于控制数据处理系统内的总线的方法和装置具有第一控制位（SAS *），第二控制位（CLA *）和至少一个终止信号（TA *，TRA *，TEA *）。 当设备以高频工作时，终端信号通常不能作为设备每个时钟沿的有效信号提供。 因此，在设备内部，终端信号在每个时钟沿不总是被采样。 相反，在主主机（10）内存在至少一个计数器，其延迟了预定数量的时钟周期的终止位的采样，以允许终止信号的时间在采样开始之前结束并变为有效的逻辑信号。 SAS *信号在主主机（10）的外部通信是否正在执行终止比特的采样，或终止比特的采样被抑制。