公开(公告)号：US20060157764A1

公开(公告)日：2006-07-20

申请号：US11373736

申请日：2006-03-09

申请人： Makarem Hussein ,  Ebrahim Andideh ,  Peter Moon ,  Daniel Diana

发明人： Makarem Hussein ,  Ebrahim Andideh ,  Peter Moon ,  Daniel Diana

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L28/55

摘要： Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

摘要翻译： 本发明的实施方案提供了一种制备铁电聚合物器件（FPMD）的方法，该方法采用避免或减少对铁电聚合物膜的不利影响的条件。 对于一个实施例，使用镶嵌图案化金属化技术。 对于一个实施例，第一金属层沉积在基板上以形成用于FPMD的底部电极。 第一金属层用选择性沉积的扩散阻挡层封盖。 然后在第一导电层上沉积一层铁电聚合物膜。 铁电聚合物膜被平坦化。 第二金属层沉积在铁电聚合物膜层上以形成FPMD的顶电极。 沉积第二金属层使得铁电聚合物膜基本上不劣化。 对于各种替代实施例，可以在远低于常规镶嵌图案化金属化工艺中采用的温度下实现各种部件工艺。

公开(公告)号：US20050082584A1

公开(公告)日：2005-04-21

申请号：US11007113

申请日：2004-12-07

申请人： Makarem Hussein ,  Ebrahim Andideh ,  Peter Moon ,  Daniel Diana

发明人： Makarem Hussein ,  Ebrahim Andideh ,  Peter Moon ,  Daniel Diana

IPC分类号： H01L21/00 ,  H01L27/115 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L28/55

摘要： Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

公开(公告)号：US20050051894A1

公开(公告)日：2005-03-10

申请号：US10659044

申请日：2003-09-09

申请人： Sarah Kim ,  Bob Martell ,  David Ayers ,  R. List ,  Peter Moon ,  Steven Towle ,  Anna George

发明人： Sarah Kim ,  Bob Martell ,  David Ayers ,  R. List ,  Peter Moon ,  Steven Towle ,  Anna George

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/36 ,  H01L23/485 ,  H01L23/498 ,  H01L23/528 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L24/12 ,  H01L21/76838 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.