公开(公告)号：US20060157764A1

公开(公告)日：2006-07-20

申请号：US11373736

申请日：2006-03-09

申请人： Makarem Hussein ,  Ebrahim Andideh ,  Peter Moon ,  Daniel Diana

发明人： Makarem Hussein ,  Ebrahim Andideh ,  Peter Moon ,  Daniel Diana

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L28/55

摘要： Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

摘要翻译： 本发明的实施方案提供了一种制备铁电聚合物器件（FPMD）的方法，该方法采用避免或减少对铁电聚合物膜的不利影响的条件。 对于一个实施例，使用镶嵌图案化金属化技术。 对于一个实施例，第一金属层沉积在基板上以形成用于FPMD的底部电极。 第一金属层用选择性沉积的扩散阻挡层封盖。 然后在第一导电层上沉积一层铁电聚合物膜。 铁电聚合物膜被平坦化。 第二金属层沉积在铁电聚合物膜层上以形成FPMD的顶电极。 沉积第二金属层使得铁电聚合物膜基本上不劣化。 对于各种替代实施例，可以在远低于常规镶嵌图案化金属化工艺中采用的温度下实现各种部件工艺。

公开(公告)号：US20050082584A1

公开(公告)日：2005-04-21

申请号：US11007113

申请日：2004-12-07

申请人： Makarem Hussein ,  Ebrahim Andideh ,  Peter Moon ,  Daniel Diana

发明人： Makarem Hussein ,  Ebrahim Andideh ,  Peter Moon ,  Daniel Diana

IPC分类号： H01L21/00 ,  H01L27/115 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L28/55

摘要： Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

公开(公告)号：US20050084985A1

公开(公告)日：2005-04-21

申请号：US10688085

申请日：2003-10-17

申请人： Makarem Hussein ,  Ebrahim Andideh ,  Peter Moon ,  Daniel Diana

发明人： Makarem Hussein ,  Ebrahim Andideh ,  Peter Moon ,  Daniel Diana

IPC分类号： H01L21/00 ,  H01L27/115 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L28/55

摘要： Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

摘要翻译： 本发明的实施方案提供了一种制备铁电聚合物器件（FPMD）的方法，该方法采用避免或减少对铁电聚合物膜的不利影响的条件。 对于一个实施例，使用镶嵌图案化金属化技术。 对于一个实施例，第一金属层沉积在基板上以形成FPMD的底部电极。 第一金属层用选择性沉积的扩散阻挡层封盖。 然后在第一导电层上沉积一层铁电聚合物膜。 铁电聚合物膜被平坦化。 第二金属层沉积在铁电聚合物膜层上以形成FPMD的顶电极。 沉积第二金属层使得铁电聚合物膜基本上不劣化。 对于各种替代实施例，可以在远低于常规镶嵌图案化金属化工艺中采用的温度下实现各种部件工艺。

公开(公告)号：US20060105100A1

公开(公告)日：2006-05-18

申请号：US11304046

申请日：2005-12-15

申请人： Daniel Diana ,  Hitesh Windlass ,  William Hicks ,  Timothy Lanfri ,  Michael Deangelis ,  Ebrahim Andideh

发明人： Daniel Diana ,  Hitesh Windlass ,  William Hicks ,  Timothy Lanfri ,  Michael Deangelis ,  Ebrahim Andideh

IPC分类号： B05D5/12

CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0021

摘要： An electrode layer for a polymer memory may be implanted to increase the number of defects in the material. As a result, that same material may be utilized for the upper and lower electrodes. In particular, defects may be introduced into a TiOx layer within the electrode to match the work functions of the upper and lower electrodes.

摘要翻译： 可以植入用于聚合物存储器的电极层以增加材料中的缺陷数量。 结果，可以使用相同的材​​料用于上电极和下电极。 特别地，可以将缺陷引入电极内的TiO 2层以匹配上电极和下电极的功函数。

公开(公告)号：US20050145907A1

公开(公告)日：2005-07-07

申请号：US10749500

申请日：2003-12-31

申请人： Hitesh Windlass ,  Ebrahim Andideh ,  Daniel Diana ,  Mark Richards ,  William Hicks

发明人： Hitesh Windlass ,  Ebrahim Andideh ,  Daniel Diana ,  Mark Richards ,  William Hicks

IPC分类号： C23C14/20 ,  C23C14/58 ,  H01L21/02 ,  H01L29/76

CPC分类号： C23C14/5833 ,  C23C14/205 ,  H01L28/55

摘要： Methods of depositing various metal layers adjacent to a ferroelectric polymer layer are disclosed. In one embodiment, a collimator may be used during a sputtering process to filter out charged particles from the material that may be deposited as a metal layer. In various embodiments, a metal layer may contain at least one of an intermetallic layer, an amorphous intermetallic layer, and an amorphized intermetallic layer.

摘要翻译： 公开了沉积与铁电聚合物层相邻的各种金属层的方法。 在一个实施例中，可以在溅射过程期间使用准直器来从可以作为金属层沉积的材料中滤出带电粒子。 在各种实施例中，金属层可以包含金属间化合物层，非晶态金属间化合物层和非晶化金属间化合物层中的至少一个。

公开(公告)号：US20060076593A1

公开(公告)日：2006-04-13

申请号：US11255282

申请日：2005-10-20

申请人： Hitesh Windlass ,  Ebrahim Andideh ,  Daniel Diana ,  Mark Richards ,  William Hicks

发明人： Hitesh Windlass ,  Ebrahim Andideh ,  Daniel Diana ,  Mark Richards ,  William Hicks

IPC分类号： H01L29/94

CPC分类号： C23C14/5833 ,  C23C14/205 ,  H01L28/55

摘要： Methods of depositing various metal layers adjacent to a ferroelectric polymer layer are disclosed. In one embodiment, a collimator may be used during a sputtering process to filter out charged particles from the material that may be deposited as a metal layer. In various embodiments, a metal layer may contain at least one of an intermetallic layer, an amorphous intermetallic layer, and an amorphized intermetallic layer.

摘要翻译： 公开了沉积与铁电聚合物层相邻的各种金属层的方法。 在一个实施例中，可以在溅射过程期间使用准直器来从可以作为金属层沉积的材料中滤出带电粒子。 在各种实施例中，金属层可以包含金属间化合物层，非晶态金属间化合物层和非晶化金属间化合物层中的至少一个。

公开(公告)号：US20050146923A1

公开(公告)日：2005-07-07

申请号：US10746173

申请日：2003-12-24

申请人： Daniel Diana ,  Douglas Janousek ,  Ebrahim Andideh ,  Mark Richards ,  Hitesh Windlass ,  Michael Deangelis

发明人： Daniel Diana ,  Douglas Janousek ,  Ebrahim Andideh ,  Mark Richards ,  Hitesh Windlass ,  Michael Deangelis

IPC分类号： G11C11/00 ,  G11C11/22

CPC分类号： G11C11/22

摘要： By using a plurality of relatively thin stacked diffusion layers interposed between a conductive line and a polymer layer, the diffusion of contaminates into a polymer layer from the conductive line may be reduced. This may reduce part failure during fatigue or disturb testing, for example, in ferroelectric polymer memories.

摘要翻译： 通过使用介于导电线和聚合物层之间的多个相对薄的堆叠扩散层，可以减少污染物从导电线扩散到聚合物层中。 这可以减少疲劳或干扰测试中的部件故障，例如在铁电聚合物存储器中。

公开(公告)号：US20050070032A1

公开(公告)日：2005-03-31

申请号：US10676795

申请日：2003-09-30

申请人： Mark Richards ,  Daniel Diana ,  Hitesh Windlass ,  Wayne Ford ,  Ebrahim Andideh

发明人： Mark Richards ,  Daniel Diana ,  Hitesh Windlass ,  Wayne Ford ,  Ebrahim Andideh

IPC分类号： G03C5/00 ,  G11C13/00 ,  H01L21/00 ,  H01L21/336 ,  H01L29/94 ,  H01L31/113

CPC分类号： G11C13/00 ,  B82Y10/00

摘要： According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.

公开(公告)号：US20050106760A1

公开(公告)日：2005-05-19

申请号：US10713307

申请日：2003-11-14

申请人： Hitesh Windlass ,  Ebrahim Andideh ,  Daniel Diana

发明人： Hitesh Windlass ,  Ebrahim Andideh ,  Daniel Diana

IPC分类号： G11C11/22 ,  H01L21/00 ,  H01L21/31 ,  H01L21/469

CPC分类号： B82Y10/00 ,  G11C11/22

摘要： Methods for improving the net remnant polarization of a polymer memory cell are disclosed. In one embodiment, the polymer material is heated above the Curie temperature of the polymer material, and the domains of the polymer material are aligned with an externally applied electric field.

摘要翻译： 公开了改善聚合物存储单元净残余极化的方法。 在一个实施方案中，将聚合物材料加热到聚合物材料的居里温度以上，并且聚合物材料的区域与外部施加的电场对准。

公开(公告)号：US20050183960A1

公开(公告)日：2005-08-25

申请号：US11112287

申请日：2005-04-21

申请人： Ebrahim Andideh ,  Daniel Diana

发明人： Ebrahim Andideh ,  Daniel Diana

IPC分类号： C25D5/02 ,  C25D7/12 ,  H01L21/00 ,  H01L21/28 ,  H01L21/288 ,  H01L21/44 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L21/288 ,  H01L21/76838 ,  H01L29/40111

摘要： Embodiments in accordance with the present invention eliminate the need for a subtractive metal patterning process to pattern the electrode above a ferroelectric polymer. Instead, a selective electroless deposition process is used. A conductive polymer is used as a seed layer for the electroless plating of the metal electrode. A cost saving is provided by eliminating the chemical costs associated with conventional resist removal processing. The methods also potentially eliminate the requirement for aggressive and environmentally unsafe chemical-based photoresist removal processes.