公开(公告)号：US08896123B2

公开(公告)日：2014-11-25

申请号：US13478482

申请日：2012-05-23

申请人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

发明人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L29/792 ,  H01L29/94

CPC分类号： H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

公开(公告)号：US08203211B2

公开(公告)日：2012-06-19

申请号：US12798525

申请日：2010-04-06

申请人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

发明人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

IPC分类号： H01L27/115 ,  H01L23/522

CPC分类号： H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

公开(公告)号：US20120228712A1

公开(公告)日：2012-09-13

申请号：US13478482

申请日：2012-05-23

申请人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

发明人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

IPC分类号： H01L27/088

CPC分类号： H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

公开(公告)号：US20140241065A1

公开(公告)日：2014-08-28

申请号：US14272765

申请日：2014-05-08

申请人： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

发明人： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

IPC分类号： G11C16/04

CPC分类号： H01L27/11582 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157

摘要： Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

摘要翻译： 非易失性存储器件利用垂直堆叠的非易失性存储器单元串（例如，NAND型串），其可选择性地耦合到衬底内的公共源极线。 该选择耦合可以由具有不同阈值电压的横向接地选择晶体管提供，这些阈值电压考虑了非垂直堆叠的非易失性存储单元串与公共源极线之间的不同横向间隔。

公开(公告)号：US20110310670A1

公开(公告)日：2011-12-22

申请号：US13219178

申请日：2011-08-26

申请人： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

发明人： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

IPC分类号： G11C16/04

CPC分类号： H01L27/11582 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157

摘要： Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

摘要翻译： 非易失性存储器件利用垂直堆叠的非易失性存储器单元串（例如，NAND型串），其可选择性地耦合到衬底内的公共源极线。 该选择耦合可以由具有不同阈值电压的横向接地选择晶体管提供，这些阈值电压考虑了非垂直堆叠的非易失性存储单元串与公共源极线之间的不同横向间隔。

公开(公告)号：US20100258947A1

公开(公告)日：2010-10-14

申请号：US12798525

申请日：2010-04-06

申请人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

发明人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

IPC分类号： H01L27/115 ,  H01L23/522

CPC分类号： H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

公开(公告)号：US08614917B2

公开(公告)日：2013-12-24

申请号：US13219178

申请日：2011-08-26

申请人： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

发明人： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

IPC分类号： G11C11/34

CPC分类号： H01L27/11582 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157

摘要： Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

公开(公告)号：US20150076587A1

公开(公告)日：2015-03-19

申请号：US14548557

申请日：2014-11-20

申请人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

发明人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

IPC分类号： H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

公开(公告)号：US10199116B2

公开(公告)日：2019-02-05

申请号：US15664303

申请日：2017-07-31

申请人： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

发明人： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US09378831B2

公开(公告)日：2016-06-28

申请号：US14820895

申请日：2015-08-07

申请人： Jinman Han ,  Sun-Il Shim ,  Donghyuk Chae ,  Jae-Hoon Jang ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

发明人： Jinman Han ,  Sun-Il Shim ,  Donghyuk Chae ,  Jae-Hoon Jang ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/16 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/34 ,  H01L27/115

CPC分类号： G11C16/14 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

摘要翻译： 非易失性存储器件，其操作方法和包括该非易失性存储器件的存储器系统。 在操作方法中，连接到位线的第一串的接地选择线可以浮置。 可以将擦除禁止电压施加到连接到位线的第二串的接地选择线。 可以将擦除操作电压施加到第一和第二串。