公开(公告)号：US11908852B2

公开(公告)日：2024-02-20

申请号：US17833531

申请日：2022-06-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-An Lai ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L27/02 ,  H01L21/8238 ,  H01L23/522 ,  H03K19/17736

CPC分类号： H01L27/0207 ,  H01L21/823871 ,  H01L23/5226 ,  H03K19/17744

摘要： An integrated circuit includes a first transistor, a horizontal routing track extending in a first direction in a first metal layer, and a via connector conductively connecting the horizontal routing track to a first terminal of the first transistor. The integrated circuit also includes a backside routing track extending in the first direction in a backside metal layer, and a backside via connector conductively connecting the backside routing track to a second terminal of the first transistor. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. In the integrated circuit, either the first terminal or the second terminal is a gate terminal of the first transistor.

公开(公告)号：US11769723B2

公开(公告)日：2023-09-26

申请号：US17237443

申请日：2021-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wei Peng ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Wei-Cheng Lin ,  Wei-An Lai

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/06

CPC分类号： H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/0688

摘要： A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

公开(公告)号：US11737254B2

公开(公告)日：2023-08-22

申请号：US17075704

申请日：2020-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Jiann-Tyng Tzeng ,  Shih-Wei Peng ,  Wei-An Lai

IPC分类号： H01L27/11 ,  H10B10/00 ,  H01L27/092 ,  G11C5/02 ,  G11C11/412

CPC分类号： H10B10/12 ,  G11C5/025 ,  G11C11/412 ,  H01L27/092

摘要： A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

公开(公告)号：US11569166B2

公开(公告)日：2023-01-31

申请号：US17123664

申请日：2020-12-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Wei-An Lai ,  Meng-Hung Shen ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768

摘要： The present disclosure provides a semiconductor structure, including a substrate, a first metal line over the substrate and extending along a first direction, a protection layer lining a sidewall of the first metal line, a second metal line above the first metal line and extending along the first direction, and a third metal line above the second metal line, extending along a second direction perpendicular to the first direction.

公开(公告)号：US20220344258A1

公开(公告)日：2022-10-27

申请号：US17237443

申请日：2021-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wei Peng ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Wei-Cheng Lin ,  Wei-An Lai

IPC分类号： H01L23/522 ,  H01L27/06 ,  H01L23/528 ,  H01L27/02

摘要： A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

公开(公告)号：US11409937B2

公开(公告)日：2022-08-09

申请号：US17131128

申请日：2020-12-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng Lin ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Lipen Yuan ,  Wei-An Lai

IPC分类号： G06F30/392 ,  H01L27/02 ,  G06F30/398

摘要： A method of manufacturing a semiconductor device that includes identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities; relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights. The method also includes replacing cells in the first row which have the H1 height with corresponding substitute cells, each substitute cell being correspondingly taller relative to the second direction and correspondingly narrower relative to the first direction, the replacing thereby increasing a density of the second row at least without substantially increasing a density of the first row.