WAFER CHIP SCALE PACKAGE
    24.
    发明申请

    公开(公告)号:US20210111136A1

    公开(公告)日:2021-04-15

    申请号:US16739578

    申请日:2020-01-10

    Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.

    WAFER CHIP SCALE PACKAGING WITH BALL ATTACH BEFORE REPASSIVATION

    公开(公告)号:US20200043778A1

    公开(公告)日:2020-02-06

    申请号:US16051590

    申请日:2018-08-01

    Abstract: Disclosed examples provide methods that include forming a conductive structure at least partially above a conductive feature of a wafer, attaching a solder ball structure to a side of the conductive structure, and thereafter forming a repassivation layer on a side of the wafer proximate the side of the conductive structure. Further examples provide microelectronic devices and integrated circuits that include a conductive structure coupled with a conductive feature of a metallization structure, a solder ball structure connected to the conductive structure, and a printed repassivation layer disposed on the side of the metallization structure proximate a side of the conductive structure.

Patent Agency Ranking