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公开(公告)号:US20240178164A1
公开(公告)日:2024-05-30
申请号:US17994446
申请日:2022-11-28
Applicant: Texas Instruments Incorporated
Inventor: Masamitsu Matsuura , Kengo Aoya , Daiki Komatsu , Ko Shibata
IPC: H01L23/00 , H01L21/768 , H01L23/48
CPC classification number: H01L24/05 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/04 , H01L24/13 , H01L24/94 , H01L27/144
Abstract: An electronic device includes a semiconductor substrate having a first conductive routing structure on a first side of the semiconductor substrate, and a low aspect ratio via opening extending from the first side to an opposite second side. The electronic device includes a transparent cover over a portion of the first side and covering the patterned first conductive routing structure, as well as an insulator layer including a photo-imageable material on the second side and along a sidewall of the via opening, and a second conductive routing structure on an outer side of the insulator layer and extending through the via opening and directly contacting a portion of the first conductive routing structure.
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公开(公告)号:US20230253281A1
公开(公告)日:2023-08-10
申请号:US17667843
申请日:2022-02-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Daiki Komatsu , Makoto Shibuya
IPC: H01L23/31 , H01L21/48 , H01L21/56 , H01L23/495
CPC classification number: H01L23/315 , H01L21/4821 , H01L21/565 , H01L23/49558 , H01L24/48
Abstract: An integrated circuit package includes a semiconductor die having a first surface and a second surface. The first surface is attached to a top surface of a die attach pad, and the second surface has a sensing area thereon. A mold compound covers or encapsulates at least a portion of the die attach pad and the semiconductor die. A channel is formed in a top portion of the mold compound. The channel extends from a first side of the mold compound to a second side of the mold compound. A cavity is formed between the channel and the sensing area so that the sensing area is exposed to the environment.
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公开(公告)号:US11217513B2
公开(公告)日:2022-01-04
申请号:US16825676
申请日:2020-03-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Daiki Komatsu , Makoto Shibuya
Abstract: An integrated circuit (IC) package includes an encapsulation package that contains an integrated circuit die attached to a lead frame. A set of contacts is formed on the package that each have an exposed contact sidewall surface and an exposed contact lower surface. A protective layer of solder wettable material covers each contact sidewall surface.
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公开(公告)号:US20210111136A1
公开(公告)日:2021-04-15
申请号:US16739578
申请日:2020-01-10
Applicant: Texas Instruments Incorporated
Inventor: Masamitsu Matsuura , Daiki Komatsu
IPC: H01L23/00 , H01L23/31 , H01L23/528
Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.
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公开(公告)号:US20200286816A1
公开(公告)日:2020-09-10
申请号:US16825676
申请日:2020-03-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Daiki Komatsu , Makoto Shibuya
IPC: H01L23/495 , H01L23/00 , H01L21/56 , H01L21/78 , H01L21/66
Abstract: An integrated circuit (IC) package includes an encapsulation package that contains an integrated circuit die attached to a lead frame. A set of contacts is formed on the package that each have an exposed contact sidewall surface and an exposed contact lower surface. A protective layer of solder wettable material covers each contact sidewall surface.
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公开(公告)号:US20200043778A1
公开(公告)日:2020-02-06
申请号:US16051590
申请日:2018-08-01
Applicant: Texas Instruments Incorporated
Inventor: Daiki Komatsu , Makoto Shibuya
IPC: H01L21/768 , H01L23/00 , H01L23/522 , H01L23/532 , H01L23/538
Abstract: Disclosed examples provide methods that include forming a conductive structure at least partially above a conductive feature of a wafer, attaching a solder ball structure to a side of the conductive structure, and thereafter forming a repassivation layer on a side of the wafer proximate the side of the conductive structure. Further examples provide microelectronic devices and integrated circuits that include a conductive structure coupled with a conductive feature of a metallization structure, a solder ball structure connected to the conductive structure, and a printed repassivation layer disposed on the side of the metallization structure proximate a side of the conductive structure.
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27.
公开(公告)号:US20190206768A1
公开(公告)日:2019-07-04
申请号:US15858962
申请日:2017-12-29
Applicant: Texas Instruments Incorporated
Inventor: Makoto Shibuya , Daiki Komatsu
IPC: H01L23/495 , H01L23/31 , H01L21/56 , H01L21/48 , H01L23/00
CPC classification number: H01L23/49541 , H01L21/4803 , H01L21/4842 , H01L21/565 , H01L21/568 , H01L23/3121 , H01L23/49503 , H01L23/49586 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/32245 , H01L2224/48091 , H01L2224/48106 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2924/14
Abstract: Leadframes, integrated circuit packaging with wettable flanks, and methods of manufacturing the same are disclosed. An example packaged device having a leadframe includes a die pad and a lead spaced apart from the die pad. The lead has a proximal end adjacent the die pad and a distal end extending away from the die pad. The lead has a thickness at the distal end that is less than a full thickness of the leadframe between a first outer surface on a die attach side of the leadframe and a second outer surface on a mounting side of the leadframe.
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