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    SEMICONDUCTOR PACKAGE WITH AN INSULATION LAYER
    2.
    发明申请
    SEMICONDUCTOR PACKAGE WITH AN INSULATION LAYER 有权

    公开(公告)号：US20250112182A1

    公开(公告)日：2025-04-03

    申请号：US18478226

    申请日：2023-09-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Masamitsu Matsuura ,  Daiki Komatsu ,  Kengo Aoya ,  Ting-Ta Yen

    IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

    Abstract: A semiconductor package includes a semiconductor wafer having a first connection pad and a second connection pad spaced apart by a semiconductor region of the semiconductor wafer. Portions of the semiconductor wafer are covered by a protective overcoat. The semiconductor package also includes a cap wafer mounted to the semiconductor wafer and overpassing the semiconductor region of the semiconductor wafer. The cap wafer extends between the first connection pad and the second connection pad of the semiconductor wafer. The semiconductor package further includes an insulation material overlaying the cap wafer. The insulation material comprising vias to the first connection pad and the second connection pad, the vias being filled with a conductive material.

    SENSOR ELECTRONIC DEVICE
    5.
    发明申请
    SENSOR ELECTRONIC DEVICE 有权

    公开(公告)号：US20250140626A1

    公开(公告)日：2025-05-01

    申请号：US18495837

    申请日：2023-10-27

    Applicant: Texas Instruments Incorporated

    Inventor： Masamitsu Matsuura ,  Daiki Komatsu ,  Kengo Aoya

    IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

    Abstract: An electronic device includes a package structure having opposite first and second sides, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, the first and second sides spaced along a third direction orthogonal to the first and second directions, and an opening extending into the first side along the third direction, a first semiconductor die having a first side exposed in the opening of the package structure and an opposite second side partially enclosed by the package structure, and a second semiconductor die electrically connected to the first semiconductor die, the second semiconductor die enclosed by the package structure and laterally spaced apart from the first semiconductor die.

    STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE
    6.
    发明申请
    STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250038009A1

    公开(公告)日：2025-01-30

    申请号：US18361747

    申请日：2023-07-28

    Applicant: Texas Instruments Incorporated

    Inventor： Kengo Aoya ,  Masamitsu Matsuura ,  Daiki Komatsu

    IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

    Abstract: A semiconductor package has a relief recess in the mold compound, extending around the perimeter over the leads. The relief recess has a relief width greater than a thickness of the leads under the relief recess. Top surfaces of the leads may be exposed at the relief recess, or may be covered by the mold compound under the relief recess. In both cases, a height difference between the mold compound under the relief recess and the leads under the relief recess is less than the thickness of the leads under the relief recess. A majority of exposed side faces of the leads are characteristic of sawn surfaces, which includes leads being free of vertical striations or having burrs along bottom edges. The semiconductor package is singulated by sawing through the leads.

    WAFER CHIP SCALE PACKAGE
    7.
    发明申请
    WAFER CHIP SCALE PACKAGE 有权

    公开(公告)号：US20240379597A1

    公开(公告)日：2024-11-14

    申请号：US18777976

    申请日：2024-07-19

    Applicant: Texas Instruments Incorporated

    Inventor： Masamitsu Matsuura ,  Daiki Komatsu

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528

    Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.

    HIGH RELIABILITY SENSOR
    8.
    发明申请
    HIGH RELIABILITY SENSOR 有权

    公开(公告)号：US20250074765A1

    公开(公告)日：2025-03-06

    申请号：US18456585

    申请日：2023-08-28

    Applicant: Texas Instruments Incorporated

    Inventor： Daiki Komatsu ,  Masamitsu Matsuura ,  Mao Sugeno

    IPC: B81B7/00 ,  B81C1/00

    Abstract: An electronic device includes first and second semiconductor dies, the first semiconductor die having: a side extending in a first plane of orthogonal first and second directions; a sensor circuit along the side; and a conductive terminal extending outward from the side along an orthogonal third direction, and the second semiconductor die bonded to the first semiconductor die and having: a bottom side; a lateral side; and an insulation layer, the bottom side spaced apart from and facing the side of the first semiconductor die to form a protected chamber for the sensor circuit, the lateral side of the second semiconductor die spaced apart from the conductive terminal along the first direction, the insulation layer extending along the lateral side of the second semiconductor die, and the insulation layer spaced apart from and facing the conductive terminal along the first direction.

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