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    PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
    23.
    发明申请
    PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE 审中-公开

    公开(公告)号：US20200089622A1

    公开(公告)日：2020-03-19

    申请号：US16694751

    申请日：2019-11-25

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung Ong

    IPC: G06F12/1045 ,  G06F15/78

    Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    24.
    发明申请
    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM 有权

    公开(公告)号：US20250103502A1

    公开(公告)日：2025-03-27

    申请号：US18976474

    申请日：2024-12-11

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/0842 ,  G06F1/14 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0888

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    Distributed mechanism for fine-grained test power control
    25.
    发明授权
    Distributed mechanism for fine-grained test power control 有权

    公开(公告)号：US12217102B2

    公开(公告)日：2025-02-04

    申请号：US17551011

    申请日：2021-12-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Devanathan Varadarajan ,  Varun Singh ,  Jose Luis Flores ,  Rejitha Nair ,  David Matthew Thompson

    IPC: G06F9/50 ,  G06F11/30 ,  G06F11/32

    Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

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