公开(公告)号：US20230043776A1

公开(公告)日：2023-02-09

申请号：US17952517

申请日：2022-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Dheera Balasubramanian SAMUDRALA ,  Duc BUI ,  Alan DAVIS

IPC: G06F9/30 ,  G11C11/409 ,  G06F12/02 ,  G06F16/31 ,  G06F16/901 ,  G06F16/41 ,  G06F9/445 ,  G06F9/38

Abstract: A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

公开(公告)号：US20210216316A1

公开(公告)日：2021-07-15

申请号：US17216821

申请日：2021-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Kai CHIRCA ,  Timothy D. ANDERSON ,  Duc BUI ,  Abhijeet A. CHACHAD ,  Son Hung TRAN

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/32 ,  G06F11/10 ,  G06F9/345

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.

公开(公告)号：US20200379762A1

公开(公告)日：2020-12-03

申请号：US16570640

申请日：2019-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Dheera Balasubramanian SAMUDRALA ,  Duc BUI ,  Alan DAVIS

IPC: G06F9/30 ,  G06F12/02 ,  G11C11/409

Abstract: A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

公开(公告)号：US20200379761A1

公开(公告)日：2020-12-03

申请号：US16570519

申请日：2019-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Dheera Balasubramanian SAMUDRALA

IPC: G06F9/30 ,  G06F12/02 ,  G11C11/409

Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to the instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The at least one operational unit is configured to perform a table write in response to a look up table write instruction by writing at least one data element from a source data register to a specified location in a specified number of at least one table.

公开(公告)号：US20200371794A1

公开(公告)日：2020-11-26

申请号：US16422688

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph ZBICIAK ,  Brett L. HUBER ,  Duc BUI

IPC: G06F9/30 ,  G06K9/62

Abstract: A method to classify source data in a processor in response to a vector floating-point classification instruction includes specifying, in respective fields of the vector floating-point classification instruction, a source register containing the source data and a destination register to store classification indications for the source data. The source register includes a plurality of lanes that each contains a floating-point value and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector floating-point classification instruction by, for each lane in the source register, classifying the floating-point value in the lane to identify a type of the floating-point value, and storing a value indicative of the identified type in the corresponding lane of the destination register.

公开(公告)号：US20200371788A1

公开(公告)日：2020-11-26

申请号：US16422501

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc BUI ,  Peter Richard DENT ,  Timothy D. ANDERSON

IPC: G06F9/30

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US20200371784A1

公开(公告)日：2020-11-26

申请号：US16422754

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Duc BUI ,  Joseph ZBICIAK

IPC: G06F9/30

Abstract: A method to scale source data in a processor in response to a vector floating-point scale instruction includes specifying a first source register containing the source data, a second source register containing scale values, and a destination register to store scaled source data. The first source register includes a plurality of lanes that each contains a floating-point value and the second source register and the destination register each includes a plurality of lanes corresponding to the lanes of the first source register. The method includes executing the vector floating-point scale instruction by, for each lane in the first source register adding the scale value in the corresponding lane of the second source register to an exponent field of the floating-point value in the lane of the first source register to create a scaled floating-point value, and storing the scaled floating-point value in the corresponding lane of the destination register.