-
公开(公告)号：US11955964B2
公开(公告)日：2024-04-09
申请号：US17169638
申请日：2021-02-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Kunal Suresh Karanjkar , Venkata Ramanan R
IPC: H03K17/693 , H03F3/72 , H03K17/00 , H03K17/10
CPC classification number: H03K17/693 , H03F3/72 , H03K17/005 , H03K17/102
Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.
-
公开(公告)号：US11848678B2
公开(公告)日：2023-12-19
申请号：US17931557
申请日：2022-09-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Venkat Ramakrishna Saripalli , Venkata Ramanan R
CPC classification number: H03K5/2481 , H03F1/0205 , H03F3/45179
Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.
-
公开(公告)号：US20230246595A1
公开(公告)日：2023-08-03
申请号：US18298626
申请日：2023-04-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Aniruddha Roy
CPC classification number: H03F1/0233 , H03F1/3205 , H03F2200/504
Abstract: A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.
-
公开(公告)号：US20230208369A1
公开(公告)日：2023-06-29
申请号：US18175828
申请日：2023-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Suresh Mallala , Nitin Agarwal
CPC classification number: H03F3/45192 , H03F3/3066 , H03F2200/372 , H03F2203/45248
Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.
-
公开(公告)号：US20220129024A1
公开(公告)日：2022-04-28
申请号：US17572692
申请日：2022-01-11
Applicant: Texas Instruments Incorporated
Inventor： Sachin Sudhir Turkewadikar , Nitin Agarwal , Madhan Radhakrishnan
IPC: G05F1/56
Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.
-
Patent Agency Ranking
公开(公告)号：US11256276B2
公开(公告)日：2022-02-22
申请号：US16689545
申请日：2019-11-20
Applicant: Texas Instruments Incorporated
Inventor： Sachin Sudhir Turkewadikar , Nitin Agarwal , Madhan Radhakrishnan
Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.
-
公开(公告)号：US11139648B2
公开(公告)日：2021-10-05
申请号：US16227656
申请日：2018-12-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumit Dubey , Nitin Agarwal
IPC: H02H3/20
Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.
-
公开(公告)号：US10917090B1
公开(公告)日：2021-02-09
申请号：US16700444
申请日：2019-12-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Kunal Suresh Karanjkar , Venkata Ramanan R
IPC: H03K17/693 , H03K17/10 , H03K17/00 , H03F3/72
Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.
-
公开(公告)号：US09716435B2
公开(公告)日：2017-07-25
申请号：US14272063
申请日：2014-05-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Madhan Radhakrishnan , Nitin Agarwal
CPC classification number: H02M3/1588 , H02M1/00 , H02M1/143 , H02M1/15 , H02M3/158 , H02M2001/0003 , H02M2001/0009 , H02M2001/0012 , Y02B70/1466
Abstract: Aspects of the present invention provide a DC/DC converter for use with a supply voltage and operable to drive a load, wherein the DC/DC converter includes a VIN node, a VOUT node, a switching component, a filter, a comparator, a current detecting component and a control component. The VIN node can receive the supply voltage and the VOUT node can provide an output voltage to drive the load. The filter electrically connects the switching component with the VOUT node. The comparator can generate a comparison signal based on the output voltage. The current detecting component can detect when a current in a direction from the filter toward the VOUT node decreases to zero. The control component can control the switching component so as to provide the output voltage at the VOUT node in a discontinuous conduction mode to drive the load.
-
公开(公告)号：US20150207405A1
公开(公告)日：2015-07-23
申请号：US14162470
申请日：2014-01-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal
CPC classification number: H03M1/70 , H02M3/157 , H03F3/45183 , H03F2203/45101 , H03F2203/45586 , H03K5/2481
Abstract: Several circuits and methods for input offset control are disclosed. In an embodiment, a input offset control circuit includes a first input circuit and a second input circuit. The first input circuit is configured to operate within first common mode voltage range, configured to provide first input current, and configured to vary the first input current upon or subsequent to a variation of a voltage level in the first common mode voltage range. The second input circuit is coupled to the first input circuit and is configured to operate within second common mode voltage range, configured to provide a second input current, and configured to vary the second input current based on variation of the voltage level in the second common mode voltage range. Upon or subsequent to increasing the common mode voltage, the first input current is reduced and the second input current is increased.
Abstract translation: 公开了用于输入偏移控制的若干电路和方法。 在一个实施例中，输入偏移控制电路包括第一输入电路和第二输入电路。 第一输入电路被配置为在第一共模电压范围内工作，被配置为提供第一输入电流，并且被配置为在第一共模电压范围内的电压电平的变化或之后改变第一输入电流。 第二输入电路耦合到第一输入电路，并且被配置为在第二共模电压范围内工作，被配置为提供第二输入电流，并且被配置为基于第二公共电压中的电压电平的变化来改变第二输入电流 模式电压范围。 在增加共模电压或随后增加共模电压时，第一输入电流减小并且第二输入电流增加。
-
-
-
-
-
-
-
-
-
Search Results
55
records
(took 0.022 seconds)
