公开(公告)号：US20190013795A1

公开(公告)日：2019-01-10

申请号：US16005673

申请日：2018-06-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  KARTHIK KHANNA S ,  Chandrasekhar Sriram ,  Rajendrakumar Joish ,  Viswanathan Nagarajan

IPC: H03H11/12 ,  H03H11/06 ,  H01P1/22

CPC classification number: H03H11/1204 ,  H01P1/22 ,  H03H11/06 ,  H03H17/02 ,  H03H2011/0494 ,  H03M1/12

Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

公开(公告)号：US20180083580A1

公开(公告)日：2018-03-22

申请号：US15824984

申请日：2017-11-28

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish

IPC: H03F3/19 ,  H03F3/45 ,  H03F3/191 ,  H03F1/02 ,  H03F1/22 ,  H03F1/32

CPC classification number: H03F3/19 ,  H03F1/0205 ,  H03F1/0277 ,  H03F1/22 ,  H03F1/223 ,  H03F1/3211 ,  H03F3/191 ,  H03F3/45 ,  H03F3/45098 ,  H03F3/45103 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/546 ,  H03F2203/45296 ,  H03F2203/45396

Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

公开(公告)号：US09813040B2

公开(公告)日：2017-11-07

申请号：US14857815

申请日：2015-09-17

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish

IPC: H01P1/22 ,  H03H7/24 ,  H03F1/56 ,  H03F1/32 ,  H03F3/45

CPC classification number: H03H7/24 ,  H01P1/22 ,  H03F1/3211 ,  H03F1/56 ,  H03F3/45 ,  H03F3/45475 ,  H03F2203/45151 ,  H03F2203/45594 ,  H03F2203/45614 ,  H03F2203/45616

Abstract: A programmable (multistep) resistor attenuator architecture (such as for input to a differential amplifier) provides cancellation for harmonic distortion currents. An attenuation node is coupled: (a) to an input node through R; (b) to a virtual ground through kR and a virtual ground switch Swf with on-resistance Rswf; and (c) to a differential ground through mR and a differential ground switch Swp with on-resistance Rswp. Swp can be sized relative to Swf such that a component Ipnf of Ipn through Rswp and mR to the attenuation node, and branching into kR and Rswf, matches (phase/magnitude), a harmonic current Ifn from the virtual ground through Rswf and kR to the attenuation node. Harmonic distortion cancelation at the virtual ground can be based on matching switches Swf and Swp and the resistors R, mR, kR, reducing sensitivity to PVT variations, input frequency and amplitude. The attenuator architecture is extendable to multistage configurations.

公开(公告)号：US20170194923A1

公开(公告)日：2017-07-06

申请号：US15464091

申请日：2017-03-20

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish

IPC: H03G1/00 ,  H04B1/10 ,  H03F3/45

CPC classification number: H03G1/0082 ,  H03F1/26 ,  H03F3/45085 ,  H03F3/45098 ,  H03F3/72 ,  H03F2200/294 ,  H03F2203/45026 ,  H03F2203/45202 ,  H03F2203/45466 ,  H03F2203/45494 ,  H03F2203/45496 ,  H03F2203/45504 ,  H03F2203/7233 ,  H03G1/0035 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3052 ,  H04B1/1036 ,  H04B1/18

Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.

公开(公告)号：US20160079949A1

公开(公告)日：2016-03-17

申请号：US14857815

申请日：2015-09-17

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish

IPC: H03H7/24 ,  H03F1/56 ,  H03F3/45

CPC classification number: H03H7/24 ,  H01P1/22 ,  H03F1/3211 ,  H03F1/56 ,  H03F3/45 ,  H03F3/45475 ,  H03F2203/45151 ,  H03F2203/45594 ,  H03F2203/45614 ,  H03F2203/45616

Abstract: A programmable (multistep) resistor attenuator includes distortion cancellation for harmonic distortion currents. The attenuator includes at last one attenuation stage coupled between a signal input node and a virtual ground node (such as an input to a differential amplifier). The attenuation node is: (a) coupled to the input node through a resistor R; (b) coupled to the virtual ground node through a resistor kR and a virtual ground switch Swf with an on resistance Rswf; and (c) coupled to a differential ground through a resistor mR and a differential ground switch Swp with an on resistance Rswp. Swp is sized relative to Swf such that, when both Swp and Swf are conducting, a component Ipnf of a current Ipn through Rswp and mR to the attenuation node and branching into kR and Rswf, matches, in phase and magnitude, a harmonic current Ifn from the virtual ground through Rswf and kR to the attenuation node, thereby substantially canceling the harmonic distortion appearing at the virtual ground. Distortion cancellation can be based on cancellation is based on matching switches Swf and Swp and the resistors R, mR, kR, and hence is insensitive to PVT variations, input frequency and amplitude. an optimum ratio of Rswp and Rswf is a function of only a ratio of resistors, and hence is insensitive to values of Rswp and Rswf. The attenuator architecture is extendable to multistage configurations.

Abstract translation: 可编程（多步）电阻衰减器包括谐波失真电流的失真消除。 衰减器包括最后一个耦合在信号输入节点和虚拟接地节点（诸如差分放大器的输入）之间的衰减级。 衰减节点为：（a）通过电阻R耦合到输入节点; （b）通过电阻kR和具有导通电阻Rswf的虚拟接地开关Swf耦合到虚拟接地节点; 和（c）通过电阻mR和具有导通电阻Rswp的差分接地开关Swp耦合到差动接地。 Swp的尺寸相对于Swf，使得当Swp和Swf都导通时，通过Rswp和mR的衰减节点的电流Ipn和分支到kR和Rswf的分量Ipnf在相位和幅度上匹配谐波电流Ifn 从虚拟地通过Rswf和kR到衰减节点，从而基本上消除出现在虚拟地面处的谐波失真。 失真消除可以基于匹配开关Swf和Swp以及电阻R，mR，kR的抵消，因此对PVT变化，输入频率和幅度不敏感。 Rswp和Rswf的最佳比值仅是电阻比的函数，因此对Rswp和Rswf的值不敏感。 衰减器架构可扩展到多级配置。