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    Memory compression operable for non-contiguous write/read addresses
    22.
    发明授权
    Memory compression operable for non-contiguous write/read addresses 有权

    公开(公告)号：US09929744B2

    公开(公告)日：2018-03-27

    申请号：US15782052

    申请日：2017-10-12

    Applicant: Texas Instruments Incorporated

    Inventor： Sundarrajan Rangachari ,  Desmond Pravin Martin Fernandes ,  Rakesh Channabasappa Yaraduyathinahalli

    IPC: G06F12/00 ,  H03M7/30

    CPC classification number: H03M7/30 ,  G06F3/06 ,  G06F13/00 ,  G06F2212/401 ,  H03M7/6047

    Abstract: Disclosed embodiments include a system having a first memory for storing a plurality of data quantities, each data quantity consisting of a first number of bits, and a second memory for storing a plurality of compressed data quantities, each compressed data quantity consisting of a second number of bits that is less than the first number of bits. The system includes circuitry for reading data quantities from the first memory and for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The circuitry for reading data quantities from the first memory is for reading along a read orientation selected from one of row-orientation or column-orientation from the first memory, and the circuitry for writing compressed data quantities in the second memory is for writing along a write orientation in the second memory that differs from the read orientation.

    Current reduction in digital circuits
    23.
    发明授权
    Current reduction in digital circuits 有权
    数字电路当前减少

    公开(公告)号：US09025705B2

    公开(公告)日：2015-05-05

    申请号：US14046479

    申请日：2013-10-04

    Applicant: Texas Instruments Incorporated

    Inventor： Sundarrajan Rangachari ,  Jaiganesh Balakrishnan

    IPC: H04L27/08 ,  H04L25/06

    CPC classification number: H04L25/061

    Abstract: A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including samples at a plurality of sample instances, the samples including a positive sample and a negative sample and represented by first plurality of bits. The biasing circuit generates a biased digital signal by adding a bias value to the digital signal so as to change the positive sample and the negative sample to first sample and second sample respectively and represented by second plurality of bits. The digital baseband circuit is configured to receive and process the biased digital signal such that reduced current consumption is realized based on a number of bit toggles in the second plurality of bits being less than a number of bit toggles in the first plurality of bits.

    Abstract translation: 数字电路包括至少一个输入节点，偏置电路和数字基带电路。 输入节点接收包括多个采样实例的采样的数字信号，采样包括正采样和负采样并由第一多个位表示。 偏置电路通过向数字信号添加偏置值来产生偏置数字信号，以分别将正采样和负采样改变为第一采样和第二采样，并由第二多位表示。 数字基带电路被配置为接收和处理偏置的数字信号，使得基于第二多个位中的多个比特切换小于第一多个比特中的比特切换的数量来实现减少的电流消耗。

    Low-complexity inverse sinc for RF sampling transmitters
    24.
    发明授权
    Low-complexity inverse sinc for RF sampling transmitters 有权

    公开(公告)号：US11757475B2

    公开(公告)日：2023-09-12

    申请号：US17492710

    申请日：2021-10-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaiganesh Balakrishnan ,  Sriram Murali ,  Sundarrajan Rangachari ,  Yeswanth Guntupalli

    IPC: H04B1/10 ,  H04B1/00

    CPC classification number: H04B1/0025 ,  H04B1/001 ,  H04B1/0042

    Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sin c response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sin c filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

    Digital clock generation with randomized division of a source clock
    26.
    发明授权
    Digital clock generation with randomized division of a source clock 有权

    公开(公告)号：US10911057B2

    公开(公告)日：2021-02-02

    申请号：US16680046

    申请日：2019-11-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sarma Sundareswara Gunturi ,  Jawaharlal Tangudu ,  Sundarrajan Rangachari

    IPC: H03L7/18 ,  H04B1/40 ,  H03K3/84

    Abstract: A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.

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