公开(公告)号：US11334354B2

公开(公告)日：2022-05-17

申请号：US16361449

申请日：2019-03-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Anderson ,  Duc Quang Bui ,  Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.

公开(公告)号：US11182200B2

公开(公告)日：2021-11-23

申请号：US15636686

申请日：2017-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Anderson ,  Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F15/76

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

公开(公告)号：US10592339B2

公开(公告)日：2020-03-17

申请号：US16133434

申请日：2018-09-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/312 ,  G06F9/34 ,  G06F11/10 ,  G06F12/02 ,  G06F11/14 ,  G06F9/345 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F13/38 ,  G06F13/40

Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

公开(公告)号：US20190026111A1

公开(公告)日：2019-01-24

申请号：US16139858

申请日：2018-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/32 ,  G06F12/0897 ,  G06F9/30 ,  G06F13/40 ,  G06F13/16 ,  G06F9/38 ,  G06F12/0815 ,  G06F9/345

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

公开(公告)号：US20190004853A1

公开(公告)日：2019-01-03

申请号：US15636686

申请日：2017-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Anderson ,  Joseph Zbiciak

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

公开(公告)号：US10083035B2

公开(公告)日：2018-09-25

申请号：US15384580

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/34 ,  G06F12/00 ,  G06F13/36 ,  G06F9/32 ,  G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0815 ,  G06F9/345

CPC classification number: G06F9/321 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0207 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/1605 ,  G06F13/4068 ,  G06F2212/452 ,  G06F2212/60

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

公开(公告)号：US20170168898A1

公开(公告)日：2017-06-15

申请号：US15384355

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1076 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30141 ,  G06F9/345 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3881 ,  G06F9/3891 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1405 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/38 ,  G06F13/40 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

公开(公告)号：US20240320094A1

公开(公告)日：2024-09-26

申请号：US18674108

申请日：2024-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F11/10 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/14 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F11/1076 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/345 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3891 ,  G06F11/00 ,  G06F11/1405 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30043 ,  G06F9/30141 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/3881 ,  G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60

Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

公开(公告)号：US20200304464A1

公开(公告)日：2020-09-24

申请号：US16786734

申请日：2020-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amritpal Singh Mundra ,  Brian J. Karguth ,  Timothy Anderson ,  Kai Chirca ,  Charles Fuoco

IPC: H04L29/06

Abstract: A flexible hybrid firewall architecture is disclosed. A system implementing such an architecture includes an access control register, a memory having at least a region to which access is controllable by the access control register, the access control register including first field that contains a privilege identifier (ID) and a plurality of additional fields, each additional field containing control bits corresponding to a respective one of a plurality of permission levels, and control circuitry that, in response to receiving a transaction containing a transaction privilege ID, a security indicator, and a privilege indicator, controls access to the region when the transaction privilege ID matches the privilege ID contained in the first field by using the control bits of a field of the additional fields that corresponds to a security level indicated by the security indicator and a privilege level indicated by the privilege indicator of the transaction.

公开(公告)号：US10318293B2

公开(公告)日：2019-06-11

申请号：US14327038

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy Anderson ,  Duc Quang Bui ,  Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data.