公开(公告)号：US10684322B2

公开(公告)日：2020-06-16

申请号：US16247271

申请日：2019-01-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G01R1/04 ,  G01R1/067

Abstract: In a method of testing a semiconductor wafer including a scribe line and multiple dies, the method includes implementing a first landing pad on the scribe line, and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip, and applying an ATE resource to the first cluster of dies.

公开(公告)号：US20190154755A1

公开(公告)日：2019-05-23

申请号：US16247271

申请日：2019-01-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/28 ,  G01R1/04 ,  G01R1/067 ,  G01R31/3185

Abstract: In a method of testing a semiconductor wafer including a scribe line and multiple dies, the method includes implementing a first landing pad on the scribe line, and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip, and applying an ATE resource to the first cluster of dies.

公开(公告)号：US10180454B2

公开(公告)日：2019-01-15

申请号：US15130429

申请日：2016-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/26 ,  G01R31/28 ,  G01R1/067 ,  G01R31/3185 ,  G01R1/04

Abstract: A method of testing a semiconductor wafer comprising a scribe line and a plurality of dies. The method includes implementing a first landing pad on the scribe line and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the plurality of dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip and applying an ATE resource to the first cluster of dies.

公开(公告)号：US10008261B2

公开(公告)日：2018-06-26

申请号：US15706901

申请日：2017-09-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vinod Menezes

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C5/14 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/065 ,  G11C11/412 ,  G11C11/413

Abstract: A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.

公开(公告)号：US09698770B1

公开(公告)日：2017-07-04

申请号：US15093343

申请日：2016-04-07

Applicant: Texas Instruments Incorporated

Inventor： Vinod Menezes

IPC: H03L7/00 ,  H03K17/22 ,  H03K5/24 ,  H03K5/04

CPC classification number: H03K17/223 ,  H03K5/04 ,  H03K5/2472

Abstract: A low power reset circuit includes a bias generator for receiving an operating voltage generated by a power supply and generating a bias voltage in response to the received operating voltage. The operation speed of a shaper for generating a shaped signal for indicating the operating voltage and the operation speed of a comparator for comparing a threshold reference voltage with the shaped signal are both controlled in response to the generated bias voltage. The comparator also generates a comparison signal for indicating a result of the comparison. In response to the comparison signal, a reset signal generator generates a reset signal for resetting protected circuitry powered by the operating voltage generated by the power supply.

公开(公告)号：US09613685B1

公开(公告)日：2017-04-04

申请号：US14940715

申请日：2015-11-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Premkumar Seetharaman ,  Vinod Menezes

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: A static random access memory (SRAM) includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller is configured to receive a precharge signal and a word line signal and identify consecutive reads from storage cells accessed via a same one of the word lines. The read controller is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a partial burst mode, precharge the bit lines no more than once during the consecutive reads and charge the same one of the word lines after each read of the consecutive reads.

公开(公告)号：US09571104B1

公开(公告)日：2017-02-14

申请号：US14886242

申请日：2015-10-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vinod Menezes

IPC: H03K19/17 ,  H03K19/177 ,  H03K19/00 ,  H03K17/22

CPC classification number: H03K19/17772 ,  H03K19/0013

Abstract: Methods and apparatus permit body biasing to be controlled for transistors of a logic device. By controlling the body biasing, transistor threshold voltages can be controlled—increased during standby modes of the logic device to reduce leakage current and decreased during active modes and to increase switching speed during the active modes. The change in the body biasing can be made relatively slowly to reduce wasted energy that would otherwise be dissipated as heat. In a method embodiment, the method includes obtaining first and second body bias slope parameters, each slope parameter defining, at least in part, a slope of a body bias voltage signal. The method includes charging a body of a transistor with a bias voltage signal per the first body bias slope parameter to lower a threshold voltage, and discharging the body per the second body bias slope parameter to decrease leakage current of the transistor.

Abstract translation: 方法和装置允许对逻辑器件的晶体管控制主体偏置。 通过控制主体偏置，可以在逻辑器件的待机模式期间控制晶体管阈值电压，以减少泄漏电流并在活动模式期间降低，并在活动模式期间提高开关速度。 身体偏置的变化可以相对较慢地减少，否则浪费的能量将以热量消散。 在方法实施例中，该方法包括获得第一和第二体偏置斜率参数，每个斜率参数至少部分地限定体偏置电压信号的斜率。 该方法包括：使用每个第一体偏置斜率参数的偏置电压信号对晶体管体进行充电以降低阈值电压;以及根据第二体偏置斜率参数对体进行放电以减小晶体管的漏电流。