公开(公告)号：US20200379031A1

公开(公告)日：2020-12-03

申请号：US16901966

申请日：2020-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/28 ,  G01R31/3185 ,  G01R1/04 ,  G01R1/067

Abstract: In a method of testing a semiconductor wafer, a probe tip contacts a pad in a scribe line space between facing sides of first and second dies. The probe tip is electrically coupled to an automated test equipment (ATE). The second die is spaced apart from the first die. The scribe line space includes an interconnect extending along at least an entire length of the facing sides of the first and second dies. The pad is electrically coupled through the interconnect to at least one of the first or second dies. With the ATE, circuitry is tested in at least one of the first or second dies. The pad is electrically coupled through the interconnect to the circuitry.

公开(公告)号：US12244304B2

公开(公告)日：2025-03-04

申请号：US18193905

申请日：2023-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vipul K. Singhal

IPC: H03K17/687

Abstract: In examples, an apparatus has input and output terminals, and includes a first transistor having a first gate, source, and drain, wherein the first source is coupled to the input terminal, and the first drain is coupled to the output terminal, a second transistor having a second gate, source, and drain, wherein the second gate is coupled to a ground terminal, and the second source is coupled to the first gate, a third transistor having a third gate, source, and drain, wherein the third gate is coupled to an enable terminal, the third source is coupled to the ground terminal, and the third drain is coupled to the second drain, and a fourth transistor having a fourth gate, source, and drain, wherein the fourth gate is coupled to the second drain, the fourth source is coupled to the second source, and the fourth drain is coupled to the input terminal.

公开(公告)号：US09496024B1

公开(公告)日：2016-11-15

申请号：US14974945

申请日：2015-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivasa Raghavan Sridhara ,  Sanjeev Kumar Suman ,  Premkumar Seetharaman ,  Keshav Bhaktavatson Chintamani ,  Atul Ramakant Lele ,  Raviprakash S. Rao ,  Parvinder Kumar Rana ,  Ajith Subramonia ,  Vipul K. Singhal ,  Malav Shrikant Shah ,  Bharath Kumar Poluri

IPC: G11C5/14 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C11/413

Abstract: A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.

Abstract translation: 芯片上的系统（SOC）包括处理器和耦合到处理器的存储器系统。 存储器系统包括静态随机存取存储器（SRAM）存储体和存储器控制器。 SRAM库包括耦合到SRAM阵列电源的第一开关和SRAM阵列中的SRAM存储单元的晶体管的源极。 SRAM库还包括耦合到NWELL电源和SRAM存储单元的大部分晶体管的第二开关。 第二开关被配置为在SRAM阵列上电期间在第一开关闭合之前关闭。

公开(公告)号：US11320478B2

公开(公告)日：2022-05-03

申请号：US16901966

申请日：2020-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R33/00 ,  G01R31/28 ,  G01R31/3185 ,  G01R1/04 ,  G01R1/067

Abstract: In a method of testing a semiconductor wafer, a probe tip contacts a pad in a scribe line space between facing sides of first and second dies. The probe tip is electrically coupled to an automated test equipment (ATE). The second die is spaced apart from the first die. The scribe line space includes an interconnect extending along at least an entire length of the facing sides of the first and second dies. The pad is electrically coupled through the interconnect to at least one of the first or second dies. With the ATE, circuitry is tested in at least one of the first or second dies. The pad is electrically coupled through the interconnect to the circuitry.

公开(公告)号：US10684322B2

公开(公告)日：2020-06-16

申请号：US16247271

申请日：2019-01-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G01R1/04 ,  G01R1/067

Abstract: In a method of testing a semiconductor wafer including a scribe line and multiple dies, the method includes implementing a first landing pad on the scribe line, and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip, and applying an ATE resource to the first cluster of dies.

公开(公告)号：US20190154755A1

公开(公告)日：2019-05-23

申请号：US16247271

申请日：2019-01-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/28 ,  G01R1/04 ,  G01R1/067 ,  G01R31/3185

Abstract: In a method of testing a semiconductor wafer including a scribe line and multiple dies, the method includes implementing a first landing pad on the scribe line, and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip, and applying an ATE resource to the first cluster of dies.

公开(公告)号：US10180454B2

公开(公告)日：2019-01-15

申请号：US15130429

申请日：2016-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/26 ,  G01R31/28 ,  G01R1/067 ,  G01R31/3185 ,  G01R1/04

Abstract: A method of testing a semiconductor wafer comprising a scribe line and a plurality of dies. The method includes implementing a first landing pad on the scribe line and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the plurality of dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip and applying an ATE resource to the first cluster of dies.