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公开(公告)号：US20140246493A1
公开(公告)日：2014-09-04
申请号：US14186029
申请日：2014-02-21
Applicant: Texas Instruments Incorporated
Inventor： Abhishek Agrawal , Yogesh Darwhekar
IPC: G06K7/10
CPC classification number: H04W4/80 , G06K7/10237 , H04B5/0056
Abstract: An electronic communication device includes an antenna configured to receive a radio frequency (RF) signal and generate a differential current signal at a first tag pin and a second tag pin. A first variable resistor is coupled to the first tag pin and a second variable resistor is coupled to the second tag pin. A mixer circuit is coupled across the first variable resistor and the second variable resistor and is configured to generate an output voltage. The output voltage is used for RF signal detection at all RF signal levels.
Abstract translation: 电子通信装置包括：天线，被配置为在第一标签引脚和第二标签引脚处接收射频（RF）信号并产生差分电流信号。 第一可变电阻器耦合到第一标签引脚，第二可变电阻器耦合到第二标签引脚。 混频器电路跨越第一可变电阻器和第二可变电阻器耦合，并且被配置为产生输出电压。 输出电压用于所有RF信号电平的RF信号检测。
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公开(公告)号：US12143114B2
公开(公告)日：2024-11-12
申请号：US18081028
申请日：2022-12-14
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Yogesh Darwhekar
Abstract: A digital-to-time converter (DTC) circuit. The DTC circuit includes a charge node. A variable current source has a source input and a source output. The source input is coupled to a DTC digital input and the source output is coupled to the charge node. A capacitor has a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is coupled to the charge node. A comparator has a first comparator input, a second comparator input, and a comparator output. The first comparator input is coupled to the charge node, the second comparator input is coupled to a reference voltage terminal, and the comparator output is coupled to a DTC output. A pre-charge circuit has a pre-charge control input and a pre-charge output. The pre-charge control input is coupled to a DTC pre-charge input and the pre-charge output is coupled to the capacitor.
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公开(公告)号：US11843392B2
公开(公告)日：2023-12-12
申请号：US17541781
申请日：2021-12-03
Applicant: Texas Instruments Incorporated
Inventor： Jayawardan Janardhanan , Yogesh Darwhekar , Subhashish Mukherjee
IPC: H03M1/10
CPC classification number: H03M1/1014
Abstract: A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.
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公开(公告)号：US20230061672A1
公开(公告)日：2023-03-02
申请号：US17462941
申请日：2021-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Arpan Sureshbhai Thakkar , Pranav Kumar , Yogesh Darwhekar
IPC: H03H11/04 , H03K5/1252 , G06F1/08
Abstract: A circuit for subharmonic detection includes in-phase and quadrature mixers, first and second filters, and a processing circuit. The in-phase mixer has a first mixer input and a first mixer output. The quadrature mixer has a second mixer input and a second mixer output, the first mixer input coupled to the second mixer input. The first filter circuit has a first filter input and a first filter output, the first filter input coupled to the first mixer output. The second filter circuit has a second filter input and a second filter output, the second filter input coupled to the second mixer output. The processing circuit has a first input and a second input, the first input of the processing circuit coupled to the first filter output, the second input of the processing circuit coupled to the second filter output. The processing circuit is configured to detect a subharmonic component of a wave at the first mixer input and the second mixer input using a first direct current (DC) component at the first input of the processing circuit and a second DC component at the second input of the processing circuit.
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公开(公告)号：US11581897B1
公开(公告)日：2023-02-14
申请号：US17377698
申请日：2021-07-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhashish Mukherjee , Jayawardan Janardhanan , Yogesh Darwhekar
Abstract: A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.
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Patent Agency Ranking
公开(公告)号：US20220365489A1
公开(公告)日：2022-11-17
申请号：US17317628
申请日：2021-05-11
Applicant: Texas Instruments Incorporated
Inventor： Yogesh Darwhekar , Subhashish Mukherjee , Narala Raghavendra Reddy
Abstract: An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.
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公开(公告)号：US10924309B2
公开(公告)日：2021-02-16
申请号：US16793486
申请日：2020-02-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yogesh Darwhekar , Pranav Kumar , Arpan Thakkar , Naveen Mahadev , Srikanth Manian
IPC: H04L27/00 , H04L27/38 , H04L27/152 , H04L27/148
Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.
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公开(公告)号：US20180183636A1
公开(公告)日：2018-06-28
申请号：US15391675
申请日：2016-12-27
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Yogesh Darwhekar , Subhashish Mukherjee
Abstract: Described examples include a method for operating a receiver including receiving an output of an in-phase IF path; receiving an output of a quadrature IF path; measuring a blocker power on a plurality of IF channels on at least one of the in-phase path and the quadrature path within a fraction of a symbol interval; selecting a selected one of the plurality of IF channels having a low blocker power as an image channel; and providing a local oscillator output to the in-phase IF path and quadrature IF path operate corresponding to the image channel, such that a frequency of the local oscillator output is changed within a fraction of the symbol interval.
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公开(公告)号：US20160165386A1
公开(公告)日：2016-06-09
申请号：US15041966
申请日：2016-02-11
Applicant: Texas Instruments Incorporated
Inventor： Abhishek Agrawal , Yogesh Darwhekar
CPC classification number: H04W4/80 , G06K7/10237 , H04B5/0056
Abstract: An electronic communication device includes an antenna configured to receive a radio frequency (RF) signal and generate a differential current signal at a first tag pin and a second tag pin. A first variable resistor is coupled to the first tag pin and a second variable resistor is coupled to the second tag pin. A mixer circuit is coupled across the first variable resistor and the second variable resistor and is configured to generate an output voltage. The output voltage is used for RF signal detection at all RF signal levels.
Abstract translation: 电子通信装置包括：天线，被配置为在第一标签引脚和第二标签引脚处接收射频（RF）信号并产生差分电流信号。 第一可变电阻器耦合到第一标签引脚，第二可变电阻器耦合到第二标签引脚。 混频器电路跨越第一可变电阻器和第二可变电阻器耦合，并且被配置为产生输出电压。 输出电压用于所有RF信号电平的RF信号检测。
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公开(公告)号：US20160103460A1
公开(公告)日：2016-04-14
申请号：US14973159
申请日：2015-12-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhishek Agrawal , Yogesh Darwhekar , Gireesh Rajendran
CPC classification number: G05F1/613 , H02M7/217 , H04B5/0031
Abstract: A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path. A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.
Abstract translation: 数字分流调节器在天线处接收射频（RF）信号，其在差分路径上产生差分输出信号。 峰值检测器耦合到天线，并通过差分路径接收差分输出信号。 第一比较器接收峰值检测器的电压输出和第一电压。 第二比较器接收峰值检测器的电压输出和第二电压。 数字状态机接收第一比较器的输出和第二比较器的输出。 多个并联NMOS晶体管接收数字状态机的输出。 数字状态机被配置为控制被激活的并联NMOS晶体管的数量，以将峰值检测器的电压输出保持在第一电压和第二电压之间。
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