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1.发明申请DIGITAL CONTROLLED OSCILLATOR AND SWITCHABLE VARACTOR FOR HIGH FREQUENCY LOW NOISE OPERATION 有权数字控制振荡器和高频低噪声操作的可切换变频器公开(公告)号：US20160112006A1
公开(公告)日：2016-04-21
申请号：US14518001
申请日：2014-10-20
Applicant: Texas Instruments Incorporated
Inventor： Gireesh Rajendran , Rakesh Kumar , Subhashish Mukherjee , Ashish Lachhwani
IPC: H03B5/12
CPC classification number: H03B5/1212 , H03B5/1228 , H03B5/1265
Abstract: Low noise switchable varactors and digital controlled oscillator (DCO) circuitry are presented for creating alternating signals at controlled frequencies, including a first transistor for selectively coupling two capacitors between varactor output nodes when a control signal is in a first state, second and third transistors for selectively coupling first and second internal nodes between the respective capacitors and the first transistor with a third internal node when the control signal is in the first state, and an inverter disconnected from the first and second internal nodes to mitigate phase noise and operable to control the voltage of the third internal node according to the control signal.
Abstract translation: 提供了低噪声可切换变容二极管和数字控制振荡器（DCO）电路，用于在受控频率下产生交变信号，包括用于在控制信号处于第一状态时选择性地耦合变容二极管输出节点之间的两个电容器的第一晶体管，第二和第三晶体管 当控制信号处于第一状态时，选择性地将相应电容器和第一晶体管之间的第一和第二内部节点耦合到第三内部节点，并且逆变器从第一和第二内部节点断开以减轻相位噪声并且可操作地控制 根据控制信号，第三内部节点的电压。
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公开(公告)号：US20150004909A1
公开(公告)日：2015-01-01
申请号：US14318606
申请日：2014-06-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhishek Agrawal , Yogesh Darwhekar , Gireesh Rajendran
CPC classification number: G05F1/613 , H02M7/217 , H04B5/0031
Abstract: A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path, A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.
Abstract translation: 数字分流调节器在天线处接收射频（RF）信号，其在差分路径上产生差分输出信号。 峰值检测器耦合到天线，并通过差分路径接收差分输出信号。第一比较器接收峰值检测器的电压输出和第一电压。 第二比较器接收峰值检测器的电压输出和第二电压。 数字状态机接收第一比较器的输出和第二比较器的输出。 多个并联NMOS晶体管接收数字状态机的输出。 数字状态机被配置为控制被激活的并联NMOS晶体管的数量，以将峰值检测器的电压输出保持在第一电压和第二电压之间。
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公开(公告)号：US09594388B2
公开(公告)日：2017-03-14
申请号：US14973159
申请日：2015-12-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhishek Agrawal , Yogesh Darwhekar , Gireesh Rajendran
CPC classification number: G05F1/613 , H02M7/217 , H04B5/0031
Abstract: A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path. A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.
Abstract translation: 数字分流调节器在天线处接收射频（RF）信号，其在差分路径上产生差分输出信号。 峰值检测器耦合到天线，并通过差分路径接收差分输出信号。 第一比较器接收峰值检测器的电压输出和第一电压。 第二比较器接收峰值检测器的电压输出和第二电压。 数字状态机接收第一比较器的输出和第二比较器的输出。 多个并联NMOS晶体管接收数字状态机的输出。 数字状态机被配置为控制被激活的并联NMOS晶体管的数量，以将峰值检测器的电压输出保持在第一电压和第二电压之间。
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4.发明申请SHARED ANTENNA SOLUTION FOR WIRELESS CHARGING AND NEAR FIELD COMMUNICATION 审中-公开用于无线充电和近场通信的共享天线解决方案公开(公告)号：US20150091502A1
公开(公告)日：2015-04-02
申请号：US14043516
申请日：2013-10-01
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Yogesh Darwhekar , Gireesh Rajendran
CPC classification number: H02J50/10 , H01Q1/38 , H01Q7/00 , H01Q21/28 , H02J7/025 , H02J17/00 , H04B5/0031 , H04B5/0037 , H04B5/0081 , Y10T29/49018
Abstract: A method of coupling a first port of a single antenna to a first coupling circuit and a second port of the single antenna to a second coupling circuit. The method includes coupling a wireless charging unit to the first coupling unit and coupling an NFC transceiver block to the second coupling circuit. The method further includes isolating the single antenna from the wireless charging unit during a time interval when the NFC transceiver block is operational and isolating the single antenna from the NFC transceiver block during a time interval when the wireless charging unit is operational.
Abstract translation: 一种将单个天线的第一端口耦合到单个天线的第一耦合电路和第二端口到第二耦合电路的方法。 该方法包括将无线充电单元耦合到第一耦合单元并将NFC收发器模块耦合到第二耦合电路。 该方法还包括在NFC收发器模块运行的时间间隔期间隔离单个天线与无线充电单元的隔离，并且在无线充电单元可操作的时间间隔期间将单个天线与NFC收发器模块隔离开。
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公开(公告)号：US08975961B2
公开(公告)日：2015-03-10
申请号：US13902389
申请日：2013-05-24
Applicant: Texas Instruments Incorporated
Inventor： Alok Prakash Joshi , Gireesh Rajendran
IPC: H03F3/45
Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.
Abstract translation: 公开了用于降低功率放大器电路中功耗的电路。 在某些实施例中，用于发射机中功率控制的电路包括耦合电路，第一功率放大器电路和第二功率放大器电路。 耦合电路包括与第一次级绕组和第二次级绕组感应地相关联的初级绕组。 耦合电路响应于初级绕组处的信号在第一次级绕组和第二次级绕组的输出端提供信号。 第一功率放大器电路与第一次级绕组的输出端耦合，第二功率放大器与第二次级绕组的输出端耦合。 第一功率放大器电路和第二功率放大器电路被配置为基于偏置电压被使能或禁用。
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Patent Agency Ranking
6.发明授权公开(公告)号：US09722536B2
公开(公告)日：2017-08-01
申请号：US14518001
申请日：2014-10-20
Applicant: Texas Instruments Incorporated
Inventor： Gireesh Rajendran , Rakesh Kumar , Subhashish Mukherjee , Ashish Lachhwani
IPC: H03B5/12
CPC classification number: H03B5/1212 , H03B5/1228 , H03B5/1265
Abstract: Low noise switchable varactors and digital controlled oscillator (DCO) circuitry are presented for creating alternating signals at controlled frequencies, including a first transistor for selectively coupling two capacitors between varactor output nodes when a control signal is in a first state, second and third transistors for selectively coupling first and second internal nodes between the respective capacitors and the first transistor with a third internal node when the control signal is in the first state, and an inverter disconnected from the first and second internal nodes to mitigate phase noise and operable to control the voltage of the third internal node according to the control signal.
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7.发明授权Method, system and apparatus for coupling multiple radio receivers to a receiving antenna 有权用于将多个无线电接收机耦合到接收天线的方法，系统和装置公开(公告)号：US08682269B1
公开(公告)日：2014-03-25
申请号：US13723884
申请日：2012-12-21
Applicant: Texas Instruments Incorporated
Inventor： Gireesh Rajendran
IPC: H04B1/16
CPC classification number: H04B1/18
Abstract: A first radio receiver may be configured to receive an RF signal from an RF port and may comprise a first cascode amplifier configured to provide a primary RF signal on a primary path for processing by the first RF receiver and a bypass RF signal on a bypass path. A second radio receiver may be configured to receive a sum of the bypass RF signal and an amplified primary RF signal. As a result, the second radio receiver is coupled to the same RF port and the signal received by the second receiver is maintained constant irrespective of the RF signal current drawn by the first receiver. The product of the impedance of the tuned load of the first radio receiver and the gain of the amplifier amplifying the primary RF signal is set to unity.
Abstract translation: 第一无线电接收机可以被配置为从RF端口接收RF信号，并且可以包括第一共源共基放大器，其被配置为在主路径上提供初级RF信号以供第一RF接收机处理，并且旁路路径上的旁路RF信号 。 第二无线电接收机可以被配置为接收旁路RF信号和放大的主RF信号的和。 结果，第二无线电接收机被耦合到相同的RF端口，并且由第二接收机接收的信号保持恒定，而与第一接收机所绘制的RF信号电流无关。 第一无线电接收机的调谐负载的阻抗和放大主RF信号的放大器的增益的乘积被设置为一。
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公开(公告)号：US20140347124A1
公开(公告)日：2014-11-27
申请号：US13902389
申请日：2013-05-24
Applicant: Texas Instruments Incorporated
Inventor： Alok Prakash Joshi , Gireesh Rajendran
IPC: H03G1/00
Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.
Abstract translation: 公开了用于降低功率放大器电路中功耗的电路。 在某些实施例中，用于发射机中功率控制的电路包括耦合电路，第一功率放大器电路和第二功率放大器电路。 耦合电路包括与第一次级绕组和第二次级绕组感应地相关联的初级绕组。 耦合电路响应于初级绕组处的信号在第一次级绕组和第二次级绕组的输出端提供信号。 第一功率放大器电路与第一次级绕组的输出端耦合，第二功率放大器与第二次级绕组的输出端耦合。 第一功率放大器电路和第二功率放大器电路被配置为基于偏置电压被使能或禁用。
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公开(公告)号：US20140312474A1
公开(公告)日：2014-10-23
申请号：US13866200
申请日：2013-04-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Alok Prakash Joshi , Gireesh Rajendran , Brian Parks
IPC: H01L23/00
CPC classification number: H01L24/49 , H01L23/3107 , H01L23/4952 , H01L24/06 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/85 , H01L2224/04042 , H01L2224/05554 , H01L2224/06135 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/49052 , H01L2224/49175 , H01L2224/73265 , H01L2224/8592 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2924/00014 , H01L2924/20752 , H01L2924/00
Abstract: A semiconductor package having a die having a plurality of electrically continuous die wire bonding sites includes a first die wire bonding site and a second die wire bonding site. The package includes a substrate having a plurality of electrically continuous substrate wire bonding sites including a first substrate wire bonding site and a second substrate wire bonding site. A first bondwire is connected between the first die wire bonding site and the first substrate wire bonding site and a second bondwire is connected between the second die wire bonding site and the second substrate wire bonding site. The first and second bondwires lie in adjacent, substantially parallel bondwire planes. The second bondwire is substantially skewed with respect to said first bondwire.
Abstract translation: 具有具有多个电连续芯线接合位置的管芯的半导体封装包括第一管芯接合位置和第二管芯接合部位。 该封装包括具有包括第一衬底引线接合位置和第二衬底引线接合部位的多个电连续衬底引线接合位置的衬底。 第一接合线连接在第一芯线接合部位和第一基板引线接合位置之间，第二接合线连接在第二芯线接合部位和第二基板引线接合部位之间。 第一和第二焊丝线位于相邻的基本上平行的接合线平面中。 第二接合线相对于所述第一接合线基本上是倾斜的。
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公开(公告)号：US20160126895A1
公开(公告)日：2016-05-05
申请号：US14529056
申请日：2014-10-30
Applicant: Texas Instruments Incorporated
Inventor： Gireesh Rajendran , Rakesh Kumar , Alok Prakask Joshi , Subhashish Mukherjee , Krishnaswamy Thiagarajan , Apu Sivadas
CPC classification number: H04L27/3405 , H03F1/0227 , H03F3/19 , H03F3/217 , H03F3/245 , H03F2200/331 , H03F2200/336 , H03F2200/451
Abstract: An I converter outputs I sign data and I magnitude data based on received I data. A Q converter outputs Q sign data and Q magnitude data based on received Q data. An I clock generates an I phase based ort the I sign data. A Q clock generates a Q phase based on the Q sign data. An I modulator generates an I magnitude pulse stream based on the I magnitude data. A Q modulator generates a Q magnitude pulse stream based on the Q magnitude data. A digital logic component generates an output signal based on the I phase, the I magnitude pulse stream, the Q phase and the Q magnitude pulse stream. A power amplifier generates an amplified signal based on the output signal.
Abstract translation: I转换器根据接收到的I数据输出I符号数据和I幅度数据。 Q转换器基于接收的Q数据输出Q符号数据和Q幅度数据。 一个I时钟产生一个I相或ort的I符号数据。 Q时钟基于Q符号数据生成Q相。 I调制器基于I幅度数据生成I幅度脉冲流。 Q调制器基于Q幅度数据产生Q幅度脉冲流。 数字逻辑部件基于I相，I幅度脉冲流，Q相和Q幅度脉冲流产生输出信号。 功率放大器基于输出信号产生放大信号。
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