公开(公告)号：US10515873B2

公开(公告)日：2019-12-24

申请号：US15698328

申请日：2017-09-07

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito Yoshimizu ,  Yoshiro Shimojo ,  Shinya Arai

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US10115733B2

公开(公告)日：2018-10-30

申请号：US15345790

申请日：2016-11-08

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20210280603A1

公开(公告)日：2021-09-09

申请号：US17328030

申请日：2021-05-24

Applicant: Toshiba Memory Corporation

Inventor： Jun Fujiki ,  Shinya Arai ,  Kotaro Fujii

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/07 ,  H01L27/11573

Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.

公开(公告)号：US11063064B2

公开(公告)日：2021-07-13

申请号：US16918005

申请日：2020-07-01

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US10923490B2

公开(公告)日：2021-02-16

申请号：US16738941

申请日：2020-01-09

Applicant: Toshiba Memory Corporation

Inventor： Kotaro Fujii ,  Jun Fujiki ,  Shinya Arai

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.

公开(公告)号：US10854534B2

公开(公告)日：2020-12-01

申请号：US16678007

申请日：2019-11-08

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito Yoshimizu ,  Yoshiro Shimojo ,  Shinya Arai

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US20200295037A1

公开(公告)日：2020-09-17

申请号：US16564783

申请日：2019-09-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun Iijima ,  Masayoshi Tagami ,  Shinya Arai ,  Takahiro Tomimatsu

IPC: H01L27/11582 ,  H01L23/00 ,  H01L23/522 ,  H01L27/11573

Abstract: In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.

公开(公告)号：US10566339B2

公开(公告)日：2020-02-18

申请号：US15691931

申请日：2017-08-31

Applicant: Toshiba Memory Corporation

Inventor： Kotaro Fujii ,  Jun Fujiki ,  Shinya Arai

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.

公开(公告)号：US10361218B2

公开(公告)日：2019-07-23

申请号：US16040292

申请日：2018-07-19

Applicant: Toshiba Memory Corporation

Inventor： Shinya Arai

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/764 ,  H01L29/06 ,  G11C16/14 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/225 ,  H01L29/167 ,  H01L21/02

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

公开(公告)号：US10109641B2

公开(公告)日：2018-10-23

申请号：US15003919

申请日：2016-01-22

Applicant: Toshiba Memory Corporation

Inventor： Shinya Arai

IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/1157 ,  H01L27/11575

Abstract: According to one embodiment, the electrode films are stacked with gaps interposed between the electrode films. The first insulating film is provided between a lowermost electrode film of the electrode films and the substrate and being a metal oxide film, a silicon carbide film, or a silicon carbonitride film. The second insulating film is provided on an uppermost electrode film of the electrode films and being a metal oxide film, a silicon carbide film, or a silicon carbonitride film. The stacked film includes a semiconductor film extending in a stacking direction of the stacked body in the stacked body, and a charge storage film provided between the semiconductor film and the electrode films.