公开(公告)号：US20220037163A1

公开(公告)日：2022-02-03

申请号：US16944653

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L21/311 ,  H01L21/67 ,  H01L21/683 ,  H01L21/02 ,  H01J37/32

Abstract: The present disclosure describes methods and systems for plasma-assisted etching of a metal oxide. The method includes modifying a surface of the metal oxide with a first gas, removing a top portion of the metal oxide by a ligand exchange reaction, and cleaning the surface of the metal oxide with a second gas.

公开(公告)号：US11024721B2

公开(公告)日：2021-06-01

申请号：US16559369

申请日：2019-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang Wu ,  Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Li-Te Lin ,  Chung-Cheng Wu ,  Gwan-Sin Chang ,  Pinyen Lin

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/49 ,  H01L29/40

Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.

公开(公告)号：US10510866B1

公开(公告)日：2019-12-17

申请号：US16007885

申请日：2018-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Zhi-Qiang Wu ,  Chung-Cheng Wu ,  Chih-Han Lin ,  Gwan-Sin Chang

IPC: H01L29/66 ,  H01L27/08 ,  H01L21/02 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311

Abstract: A semiconductor structure is disclosed that includes the fin structure and the plurality of gates. The plurality of gates disposed with respect to the fin structure and including the first gate, the second gate, and the third gate. The spacing between the first gate and the second gate is smaller than the spacing between the second gate and the third gate. The second gate is disposed between the first gate and the third gate. The foot portion of the first gate, facing the second gate, and the first foot portion of the second gate, facing the first gate, have no lateral extension. The second foot portion of the second gate, facing the third gate, and the foot portion of the third gate, facing the second gate, have no lateral extension and/or cut.

公开(公告)号：US10453925B2

公开(公告)日：2019-10-22

申请号：US15089153

申请日：2016-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsuji Ueno ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L29/00 ,  H01L29/167 ,  H01L21/02 ,  C23C16/02 ,  C30B25/18 ,  C30B29/06 ,  C23C16/44 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

公开(公告)号：US10164096B2

公开(公告)日：2018-12-25

申请号：US14833022

申请日：2015-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kun-Mu Li ,  Ming-Hua Yu ,  Tsz-Mei Kwok ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/165

Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

公开(公告)号：US11594616B2

公开(公告)日：2023-02-28

申请号：US17409195

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/02

Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

公开(公告)号：US11456360B2

公开(公告)日：2022-09-27

申请号：US15929722

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsuji Ueno ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L29/00 ,  H01L29/167 ,  H01L21/02 ,  C23C16/02 ,  C30B25/18 ,  C30B29/06 ,  C23C16/44 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

公开(公告)号：US11276604B1

公开(公告)日：2022-03-15

申请号：US17081709

申请日：2020-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chansyun David Yang ,  Chan-Lon Yang ,  Keh-Jeng Chang ,  Perng-Fei Yuh

IPC: H01L21/687 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/311

Abstract: The present disclosure describes methods and systems for radical-activated etching of a metal oxide. The system includes a chamber, a wafer holder configured to hold a wafer with a metal oxide disposed thereon, a first gas line fluidly connected to the chamber and configured to deliver a gas to the chamber, a plasma generator configured to generate a plasma from the gas, a grid system between the plasma generator and the wafer holder and configured to increase a kinetic energy of ions from the plasma, a neutralizer between the grid system and the wafer holder and configured to generate electrons and neutralize the ions to generate radicals, and a second gas line fluidly connected to the chamber and configured to deliver a precursor across the wafer. The radicals facilitate etching of the metal oxide by the precursor.

公开(公告)号：US11150559B2

公开(公告)日：2021-10-19

申请号：US16940351

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: G03F7/20

Abstract: A method for generating an extreme ultraviolet (EUV) radiation includes simultaneously irradiating two or more target droplets with laser light in an EUV radiation source apparatus to produce EUV radiation and collecting and directing the EUV radiation produced from the two or more target droplet by an imaging mirror.

公开(公告)号：US11114547B2

公开(公告)日：2021-09-07

申请号：US16573334

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/02

Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.