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    POWER RAILS FOR STACKED SEMICONDUCTOR DEVICE
    4.
    发明申请
    POWER RAILS FOR STACKED SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220059414A1

    公开(公告)日：2022-02-24

    申请号：US16997062

    申请日：2020-08-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chansyun David YANG ,  Keh-Jeng Chang ,  Chan-Lon Yang

    IPC: H01L21/84 ,  H01L21/768 ,  H01L21/762 ,  H01L23/528 ,  H01L27/12 ,  H01L23/522

    Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

    TRANSISTOR SPACER STRUCTURES
    7.
    发明公开
    TRANSISTOR SPACER STRUCTURES 审中-公开

    公开(公告)号：US20230387257A1

    公开(公告)日：2023-11-30

    申请号：US18447680

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chansyun David YANG

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51

    CPC classification number: H01L29/6656 ,  H01L29/785 ,  H01L21/02126 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/515

    Abstract: The present disclosure describes a method for forming gate spacer structures with air-gaps to reduce the parasitic capacitance between the transistor's gate structures and the source/drain contacts. In some embodiments, the method includes forming a gate structure on a substrate and a spacer stack on sidewall surfaces of the gate structure—where the spacer stack comprises an inner spacer layer in contact with the gate structure, a sacrificial spacer layer on the inner spacer layer, and an outer spacer layer on the sacrificial spacer layer. The method further includes removing the sacrificial spacer layer to form an opening between the inner and outer spacer layers, depositing a polymer material on top surfaces of the inner and outer spacer layers, etching top sidewall surfaces of the inner and outer spacer layers to form a tapered top portion, and depositing a seal material.

    STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH METAL GATE STACK
    10.
    发明申请
    STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH METAL GATE STACK 有权

    公开(公告)号：US20210119012A1

    公开(公告)日：2021-04-22

    申请号：US16657224

    申请日：2019-10-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chansyun David YANG ,  Li-Te LIN

    IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423

    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the dummy gate stack. The spacer element has an inner spacer and a dummy spacer, and the inner spacer is between the dummy spacer and the dummy gate stack. The method also includes forming a dielectric layer to surround the spacer element and the dummy gate stack and replacing the dummy gate stack with a metal gate stack. The method further includes removing the dummy spacer of the spacer element to form a recess between the inner spacer and the dielectric layer. In addition, the method includes forming a sealing element to seal the recess such that a sealed hole is formed between the metal gate stack and the dielectric layer.

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