公开(公告)号：US20230092361A1

公开(公告)日：2023-03-23

申请号：US17994548

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Kung-Chen Yeh ,  Li-Chung Kuo ,  Pu Wang ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/498 ,  H01L21/78

Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

公开(公告)号：US11600595B2

公开(公告)日：2023-03-07

申请号：US16936433

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ching Shih ,  Chih-Wei Wu ,  Szu-Wei Lu

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor package includes semiconductor bridge, first and second multilayered structures, first encapsulant, and a pair of semiconductor dies. Semiconductor dies of the pair include semiconductor substrate and conductive pads disposed at front surface of semiconductor substrate. Semiconductor bridge electrically interconnects the pair of semiconductor dies. First multilayered structure is disposed on rear surface of one semiconductor die. Second multilayered structure is disposed on rear surface of the other semiconductor die. First encapsulant laterally wraps first multilayered structure, second multilayered structure and the pair of semiconductor dies. Each one of first multilayered structure and second multilayered structure includes a top metal layer, a bottom metal layer, and an intermetallic layer. Each one of first multilayered structure and second multilayered structure has surface coplanar with surface of first encapsulant. The top metal layers, the bottom metal layers, and the intermetallic layers are in contact with the first encapsulant.

公开(公告)号：US11488882B2

公开(公告)日：2022-11-01

申请号：US16989047

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H01L23/00 ,  H01L23/16 ,  H01L23/544 ,  H01L23/10 ,  H01L23/433 ,  H01L23/28 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/14 ,  H01L21/48 ,  H01L21/768 ,  H01L21/78 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/60

Abstract: A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

公开(公告)号：US11482508B2

公开(公告)日：2022-10-25

申请号：US16934041

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ching Shih ,  Chih-Wei Wu ,  Szu-Wei Lu

IPC: H01L23/49 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

Abstract: A manufacturing method of a semiconductor package includes the following steps. A chip is provided. The chip has an active surface and a rear surface opposite to the active surface. The chip includes conductive pads disposed at the active surface. A first solder-containing alloy layer is formed on the rear surface of the chip. A second solder-containing alloy layer is formed on a surface and at a location where the chip is to be attached. The chip is mounted to the surface and the first solder-containing alloy layer is aligned with the second solder-containing alloy layer. A reflow step is performed on the first and second solder-containing alloy layers to form a joint alloy layer between the chip and the surface.

公开(公告)号：US11270976B2

公开(公告)日：2022-03-08

申请号：US16454098

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Hang Liao ,  Chih-Wei Wu ,  Jing-Cheng Lin ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsulant. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.

公开(公告)号：US20220013492A1

公开(公告)日：2022-01-13

申请号：US16924147

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Chih-Wei Wu ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Cheng-Chieh Li

IPC: H01L23/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first and second package components stacked upon and electrically connected to each other. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps, and dimensions of the first and second conductive bumps are less than those of the third and fourth conductive bumps. The semiconductor package includes a first joint structure partially wrapping the first conductive bump and the third conductive bump, and a second joint structure partially wrapping the second conductive bump and the fourth conductive bump. A curvature of the first joint structure is different from a curvature of the second joint structure.

公开(公告)号：US20210193542A1

公开(公告)日：2021-06-24

申请号：US16721829

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hua Chang ,  Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

Abstract: A package structure includes an interposer, a die and a conductive terminal. The interposer includes an encapsulant substrate, a through via and an interconnection structure. The through via is embedded in the encapsulant substrate. The interconnection structure is disposed on a first side of the encapsulant substrate and electrically connected to the through via. The die is electrically bonded to the interposer and disposed over the interconnection structure and the first side of the encapsulant substrate. The conductive terminal is disposed on a second side of the encapsulant substrate vertically opposite to the first side, and electrically connected to the interposer and the die.

公开(公告)号：US20210118817A1

公开(公告)日：2021-04-22

申请号：US17113396

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Li-Chung Kuo ,  Pu Wang ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Kung-Chen Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/498 ,  H01L21/78

Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

公开(公告)号：US20210082870A1

公开(公告)日：2021-03-18

申请号：US16572628

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Hsien-Ju Tsou

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/66 ,  H01L21/56 ,  H01L21/78

Abstract: A shift control method in manufacture of semiconductor device includes at least the following step. An overlay offset of a first target of a semiconductor die and a second target of the semiconductor die is determined, where the second target is disposed on the first target. The semiconductor die is placed over a carrier, where placing the semiconductor die includes feeding back the overlay offset to result in a positional control of the semiconductor die. The semiconductor die is post processed to form a semiconductor device. Other shift control methods in manufacture of semiconductor device are also provided.

公开(公告)号：US20210028081A1

公开(公告)日：2021-01-28

申请号：US17068064

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/18

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.