公开(公告)号：US12015023B2

公开(公告)日：2024-06-18

申请号：US17355433

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/81

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US11990443B2

公开(公告)日：2024-05-21

申请号：US17226643

申请日：2021-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Shu Chia Hsu ,  Yu-Yun Huang ,  Wen-Yao Chang ,  Yu-Jen Cheng

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/08225 ,  H01L2224/16227 ,  H01L2224/17517 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/3511

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

公开(公告)号：US20240162166A1

公开(公告)日：2024-05-16

申请号：US18422550

申请日：2024-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hui Huang ,  Da-Cyuan Yu ,  Kuan-Yu Huang ,  Pai Yuan Li ,  Hsiang-Fan Lee

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/3733 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L23/367 ,  H01L24/16 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2224/83951 ,  H01L2224/92225 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/165 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/35121

Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

公开(公告)号：US11699674B2

公开(公告)日：2023-07-11

申请号：US17409007

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Li-Chung Kuo ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Tsung-Yu Chen ,  Chien-Yuan Huang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/32 ,  H01L21/60

CPC classification number: H01L24/27 ,  H01L23/32 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L2021/60097

Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

公开(公告)号：US20220013492A1

公开(公告)日：2022-01-13

申请号：US16924147

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Chih-Wei Wu ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Cheng-Chieh Li

IPC: H01L23/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first and second package components stacked upon and electrically connected to each other. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps, and dimensions of the first and second conductive bumps are less than those of the third and fourth conductive bumps. The semiconductor package includes a first joint structure partially wrapping the first conductive bump and the third conductive bump, and a second joint structure partially wrapping the second conductive bump and the fourth conductive bump. A curvature of the first joint structure is different from a curvature of the second joint structure.

公开(公告)号：US20210375711A1

公开(公告)日：2021-12-02

申请号：US16885304

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Wei Shen ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: Semiconductor package includes interposer, dies, encapsulant. Each die includes active surface, backside surface, side surfaces. Backside surface is opposite to active surface. Side surfaces join active surface to backside surface. Encapsulant includes first material and laterally wraps dies. Dies are electrically connected to interposer and disposed side by side on interposer with respective backside surfaces facing away from interposer. At least one die includes an outer corner. A rounded corner structure is formed at the outer corner. The rounded corner structure includes second material different from first material. The outer corner is formed by backside surface and a pair of adjacent side surfaces of the at least one die. The side surfaces of the pair have a common first edge. Each side surface of the pair does not face other dies and has a second edge in common with backside surface of the at least one die.

公开(公告)号：US11156772B2

公开(公告)日：2021-10-26

申请号：US16995145

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Pin-Tso Lin ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/136 ,  G02B6/122

Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.

公开(公告)号：US20210320097A1

公开(公告)日：2021-10-14

申请号：US17355433

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L25/18

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US20210225806A1

公开(公告)日：2021-07-22

申请号：US16903392

申请日：2020-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Wei Shen ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31

Abstract: A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant. The electrical connectors are disposed on the protection layer, wherein the interconnection structure is electrically connected to the circuit substrate through the plurality of electrical connectors.

公开(公告)号：US20210018678A1

公开(公告)日：2021-01-21

申请号：US16995145

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Pin-Tso Lin ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/136 ,  G02B6/122

Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.