公开(公告)号：US10923438B2

公开(公告)日：2021-02-16

申请号：US16396001

申请日：2019-04-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Fu Tsai ,  Kung-Chen Yeh ,  I-Ting Huang ,  Shih-Ting Lin ,  Szu-Wei Lu

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/544 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00 ,  H01L25/18

摘要： A package structure and method for forming the same are provided. The method includes forming a through substrate via structure in a substrate, and forming a first trench in the substrate. The method includes stacking a first stacked die package structure over the substrate using a plurality of first bonding structures. The first bonding structures are between the substrate and the first stacked die package structure, and a there is plurality of cavities between two adjacent first bonding structures. The method also includes forming an underfill layer over the first stacked die package structure and in the cavities, and the underfill layer is formed in a portion of the first trench. The method further includes forming a package layer over the underfill layer.

公开(公告)号：US20240234210A1

公开(公告)日：2024-07-11

申请号：US18151643

申请日：2023-01-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jen-Chun Liao ,  Yen-Hung Chen ,  Ching-Hua Hsieh ,  Sung-Yueh Wu ,  Chih-Wei Lin ,  Kung-Chen Yeh

IPC分类号： H01L21/822 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L21/822 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/10156 ,  H01L2924/10157

摘要： An integrated circuit package including integrated circuit dies and a method of forming are provided. The integrated circuit package may include a first integrated circuit die and a second integrated circuit die bonded to the first integrated circuit die. The first integrated circuit die may include a first substrate, a first interconnect structure, and a first bonding layer. The first interconnect structure may be between the first bonding layer and the first substrate. The second integrated circuit die may include a second substrate, a second interconnect structure, and a second bonding layer. The second interconnect structure may be between the second bonding layer and the second substrate. A first surface of the first bonding layer may be in direct contact with a first surface of the second bonding layer. A sidewall the first bonding layer and the first surface of the second bonding layer may form a first acute angle.

公开(公告)号：US11990429B2

公开(公告)日：2024-05-21

申请号：US17994548

申请日：2022-11-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Wei Wu ,  Ying-Ching Shih ,  Kung-Chen Yeh ,  Li-Chung Kuo ,  Pu Wang ,  Szu-Wei Lu

IPC分类号： H01L23/00 ,  H01L21/3105 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L23/562 ,  H01L21/31053 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/18 ,  H01L25/50

摘要： A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

公开(公告)号：US20210202436A1

公开(公告)日：2021-07-01

申请号：US16888868

申请日：2020-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kung-Chen Yeh ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L21/268 ,  H01L21/304

摘要： A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

公开(公告)号：US20230092361A1

公开(公告)日：2023-03-23

申请号：US17994548

申请日：2022-11-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Wei Wu ,  Ying-Ching Shih ,  Kung-Chen Yeh ,  Li-Chung Kuo ,  Pu Wang ,  Szu-Wei Lu

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/498 ,  H01L21/78

摘要： A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

公开(公告)号：US20210118817A1

公开(公告)日：2021-04-22

申请号：US17113396

申请日：2020-12-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Wei Wu ,  Li-Chung Kuo ,  Pu Wang ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Kung-Chen Yeh

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/498 ,  H01L21/78

摘要： A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

公开(公告)号：US20240071849A1

公开(公告)日：2024-02-29

申请号：US17822476

申请日：2022-08-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jian-You Chen ,  Kuan-Yu Huang ,  Li-Chung Kuo ,  Chen-Hsuan Tsai ,  Kung-Chen Yeh ,  Hsien-Ju Tsou ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC分类号： H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/16 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/16227

摘要： A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.

公开(公告)号：US11164824B2

公开(公告)日：2021-11-02

申请号：US16865432

申请日：2020-05-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Fu Tsai ,  Kung-Chen Yeh ,  Li-Chung Kuo ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

摘要： A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.

公开(公告)号：US11515267B2

公开(公告)日：2022-11-29

申请号：US17113396

申请日：2020-12-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Wei Wu ,  Li-Chung Kuo ,  Pu Wang ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Kung-Chen Yeh

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/498 ,  H01L21/78

摘要： A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

公开(公告)号：US11508692B2

公开(公告)日：2022-11-22

申请号：US16888868

申请日：2020-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kung-Chen Yeh ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L21/268

摘要： A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.