公开(公告)号：US20200279812A1

公开(公告)日：2020-09-03

申请号：US16875060

申请日：2020-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiranmay BISWAS ,  Kuo-Nan YANG ,  Chung-Hsing WANG

IPC: H01L23/528 ,  H01L23/50 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer, a plurality of third power lines formed in a second metal layer and a plurality of fourth power lines formed in the second metal layer. The second power lines are parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. The third power lines are perpendicular to the first power lines. The fourth power lines are parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. A first power pitch between two adjacent third power lines is greater than a second power pitch between two adjacent fourth power lines.

公开(公告)号：US20200226229A1

公开(公告)日：2020-07-16

申请号：US16586658

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Hua LIU ,  Yun-Xiang LIN ,  Yuan-Te HOU ,  Chung-Hsing WANG

IPC: G06F17/50

Abstract: A method is utilized to calculate a boundary leakage in a semiconductor device. A boundary is detected between a first cell and a second cell, which the first cell and the second cell are abutted to each other around the boundary. Attributes associated with cell edges of the first cell and the second cell are identified. A cell abutment case is identified based on the attributes associated with the cell edges of the first cell and the second cell. An expected boundary leakage between the first cell and the second cell is calculated based on leakage current values associated with the cell abutment case and leakage probabilities associated with the cell abutment case.

公开(公告)号：US20190108306A1

公开(公告)日：2019-04-11

申请号：US16214243

申请日：2018-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen LIN ,  Ming-Hsien LIN ,  Kuo-Nan YANG ,  Chung-Hsing WANG

IPC: G06F17/50

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

公开(公告)号：US20180357351A1

公开(公告)日：2018-12-13

申请号：US15882288

申请日：2018-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung LIN ,  Chung-Hsing WANG ,  Yuan-Te HOU

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/02

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.

公开(公告)号：US20180166386A1

公开(公告)日：2018-06-14

申请号：US15651165

申请日：2017-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiranmay BISWAS ,  Kuo-Nan YANG ,  Chung-Hsing WANG

IPC: H01L23/528 ,  G06F17/50 ,  H01L23/50

Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer and parallel to the first power lines, a plurality of third power lines formed in a second metal layer, and a plurality of fourth power lines formed in the second metal layer and parallel to the third power lines. The first and second power lines are interlaced in the first metal layer. The third and fourth power lines are interlaced in the second metal layer. Distances from the individual first power line to the two adjacent second power lines are the same, and distances from the individual third power line to the two adjacent fourth power lines are different.

公开(公告)号：US20210264093A1

公开(公告)日：2021-08-26

申请号：US17315023

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Hua LIU ,  Yun-Xiang LIN ,  Yuan-Te HOU ,  Chung-Hsing WANG

IPC: G06F30/398 ,  G06F30/367 ,  G06F30/20 ,  G06F30/39

Abstract: A system includes a library, a processor and an output interface. The library contains at least one leakage lookup table related to leakage current values for different cell abutment cases of abutted cells in a semiconductor device. The cell abutment cases are associated with terminal types of cell edges of the abutted cells. The processor is configured to perform an analysis to detect boundaries between the abutted cells, identify attributes associated with the terminal types of the cell edges, identify the cell abutment cases based on the attributes, and calculate maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases. The output interface is for outputting boundary leakages corresponding to the maximal boundary leakages in the semiconductor device. A method is also disclosed herein.

公开(公告)号：US20210217743A1

公开(公告)日：2021-07-15

申请号：US17214703

申请日：2021-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan CHANG ,  Kuo-Nan YANG ,  Chung-Hsing WANG ,  Lee-Chung LU ,  Sheng-Fong CHEN ,  Po-Hsiang HUANG ,  Hiranmay BISWAS ,  Sheng-Hsiung CHEN ,  Aftab Alam KHAN

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/118 ,  G06F30/394

Abstract: A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.

公开(公告)号：US20180210993A1

公开(公告)日：2018-07-26

申请号：US15723308

申请日：2017-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung LIN ,  Yuan-Te HOU ,  Chung-Hsing WANG

IPC: G06F17/50

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes forming a first partition by selecting at least one in-boundary PG cell from the group of PG cells, adding at least one out-boundary PG cell from the group of PG cells into the first partition, forming a second partition by selecting the remaining in-boundary PG cells and the remaining out-boundary PG cells in the group of PG cells, calculating the total area of the in-boundary PG cells in the first partition, calculating the total area of the out-boundary PG cells in the first partition, calculating the total area of the in-boundary PG cells in the second partition, calculating the total area of the out-boundary PG cells in the second partition, and calculating the difference between the total areas of in-boundary PG cells in the first partition and the out-boundary PG cells in the first partition.

公开(公告)号：US20180173832A1

公开(公告)日：2018-06-21

申请号：US15703781

申请日：2017-09-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ravi Babu PITTU ,  Chung-Hsing WANG ,  Sung-Yen YEH ,  Li Chung HSU

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5036 ,  G06F17/5068 ,  G06F2217/84

Abstract: A method includes generating a first timing library for a first set of circuit elements for a first set of input parameters. Generating the first timing library includes determining device characteristics for each of the circuit elements in the first set of circuit elements and storing the determined device characteristics in a database. A second timing library is generated for a second set of circuit elements for a second set of input parameters. The second timing library is generated by using one or more of the determined device characteristics previously stored in the database. A circuit is formed on a substrate. The circuit includes at least one of the first set of circuit elements or the second set of circuit elements.

公开(公告)号：US20170169154A1

公开(公告)日：2017-06-15

申请号：US14967061

申请日：2015-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Hung LIN ,  Chung-Hsing WANG ,  Chin-Chou LIU ,  Chi-Wei HU

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F17/509

Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.