公开(公告)号：US09972571B1

公开(公告)日：2018-05-15

申请号：US15484837

申请日：2017-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L27/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H03K19/20 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/088

CPC classification number: H01L23/5283 ,  H01L21/768 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/66545 ,  H03K19/20

Abstract: The semiconductor structure includes a semiconductor substrate; field-effect devices disposed on the semiconductor substrate, wherein the field-effect devices include gates with elongated shape oriented in a first direction; a first metal layer disposed over the gates; a second metal layer disposed over the first metal layer; and a third metal layer disposed over the second metal layer. The first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction. The second metal layer includes a plurality of second metal lines oriented in the first direction. The third metal layer includes a plurality of third metal lines oriented in the second direction. The first metal lines have a first thickness, the second metal lines have a second thickness, the third metal lines have a third thickness, and the second thickness is less than the first thickness and the third thickness.

公开(公告)号：US09917084B2

公开(公告)日：2018-03-13

申请号：US15090202

申请日：2016-04-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49

Abstract: A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

公开(公告)号：US12041761B2

公开(公告)日：2024-07-16

申请号：US18182489

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang ,  Ren-Fen Tsui ,  Shih-Chi Fu ,  Yen-Huei Chen

IPC: H10B10/00 ,  G11C11/418 ,  H01L23/528 ,  H01L27/02

CPC classification number: H10B10/12 ,  G11C11/418 ,  H01L23/528 ,  H01L27/0207 ,  H10B10/18

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

公开(公告)号：US20210305260A1

公开(公告)日：2021-09-30

申请号：US17345309

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang ,  Ren-Fen Tsui ,  Shih-Chi Fu ,  Yen-Huei Chen

IPC: H01L27/11 ,  G11C11/418 ,  H01L23/528 ,  H01L27/02

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

公开(公告)号：US20210043764A1

公开(公告)日：2021-02-11

申请号：US17068162

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw

IPC: H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L21/762 ,  H01L23/522 ,  H01L21/768 ,  H01L29/45 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/321 ,  H01L29/40 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/165 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

公开(公告)号：US20200083165A1

公开(公告)日：2020-03-12

申请号：US16682795

申请日：2019-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L23/528 ,  H03K19/20 ,  H01L29/06 ,  H01L27/1157 ,  H01L27/088 ,  H01L27/02 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/11 ,  H01L21/768

Abstract: The semiconductor structure includes a plurality of FETs disposed on a semiconductor substrate, the FETs including gates with elongated shape oriented in a first direction; a first metal layer of first metal lines disposed over the gates and oriented in a second direction perpendicular to the first direction; a second metal layer of second metal lines disposed over the first metal layer and oriented in the first direction; and a third metal layer of third metal lines oriented in the second direction and disposed over the second metal layer. The first metal lines have a first pitch P1; the second metal lines have a second pitch P2; the third metal lines have a third pitch P3; and the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2.

公开(公告)号：US10515961B2

公开(公告)日：2019-12-24

申请号：US16370330

申请日：2019-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L27/02

Abstract: A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

公开(公告)号：US20190304900A1

公开(公告)日：2019-10-03

申请号：US15938484

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L23/522 ,  G06F17/50 ,  H01L21/768 ,  H01L23/528

Abstract: Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

公开(公告)号：US10269797B2

公开(公告)日：2019-04-23

申请号：US15886645

申请日：2018-02-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L27/02

Abstract: A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

公开(公告)号：US09947657B2

公开(公告)日：2018-04-17

申请号：US15090202

申请日：2016-04-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0207 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

Abstract: A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.