公开(公告)号：US12041761B2

公开(公告)日：2024-07-16

申请号：US18182489

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang ,  Ren-Fen Tsui ,  Shih-Chi Fu ,  Yen-Huei Chen

IPC: H10B10/00 ,  G11C11/418 ,  H01L23/528 ,  H01L27/02

CPC classification number: H10B10/12 ,  G11C11/418 ,  H01L23/528 ,  H01L27/0207 ,  H10B10/18

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

公开(公告)号：US11940737B2

公开(公告)日：2024-03-26

申请号：US17315087

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsueh-Yi Chung ,  Yung-Cheng Chen ,  Fei-Gwo Tsai ,  Chi-Hung Liao ,  Shih-Chi Fu ,  Wei-Ti Hsu ,  Jui-Ping Chuang ,  Tzong-Sheng Chang ,  Kuei-Shun Chen ,  Meng-Wei Chen

IPC: G03F7/20 ,  G03F1/50 ,  G03F1/68 ,  G03F1/70 ,  G03F1/78 ,  G03F7/00 ,  H01L21/66

CPC classification number: G03F7/70433 ,  G03F1/50 ,  G03F1/68 ,  G03F1/70 ,  G03F1/78 ,  G03F7/20 ,  G03F7/70141 ,  G03F7/70158 ,  G03F7/70716 ,  H01L22/30

Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

公开(公告)号：US20210305260A1

公开(公告)日：2021-09-30

申请号：US17345309

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang ,  Ren-Fen Tsui ,  Shih-Chi Fu ,  Yen-Huei Chen

IPC: H01L27/11 ,  G11C11/418 ,  H01L23/528 ,  H01L27/02

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

公开(公告)号：US10534272B2

公开(公告)日：2020-01-14

申请号：US16127017

申请日：2018-09-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsueh-Yi Chung ,  Yung-Cheng Chen ,  Fei-Gwo Tsai ,  Chi-Hung Liao ,  Shih-Chi Fu ,  Wei-Ti Hsu ,  Jui-Ping Chuang ,  Tzong-Sheng Chang ,  Kuei-Shun Chen ,  Meng-Wei Chen

IPC: G03B27/32 ,  G03F7/20 ,  G03F1/70 ,  G03F1/78 ,  G03F1/50 ,  G03F1/68 ,  H01L21/66

Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

公开(公告)号：US11605637B2

公开(公告)日：2023-03-14

申请号：US17345309

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang ,  Ren-Fen Tsui ,  Shih-Chi Fu ,  Yen-Huei Chen

IPC: H01L27/11 ,  G11C11/418 ,  H01L23/528 ,  H01L27/02

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

公开(公告)号：US11275301B2

公开(公告)日：2022-03-15

申请号：US16530218

申请日：2019-08-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Tsung Shih ,  Tsung-Chih Chien ,  Shih-Chi Fu ,  Chi-Hua Fu ,  Kuotang Cheng ,  Bo-Tsun Liu ,  Tsung Chuan Lee

IPC: G03F1/22 ,  G03F1/38 ,  G03F1/46 ,  G03F7/20

Abstract: An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

公开(公告)号：US20230225100A1

公开(公告)日：2023-07-13

申请号：US18182489

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang ,  Ren-Fen Tsui ,  Shih-Chi Fu ,  Yen-Huei Chen

IPC: H10B10/00

CPC classification number: H10B10/18

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

公开(公告)号：US11094802B2

公开(公告)日：2021-08-17

申请号：US16507951

申请日：2019-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Wen Hsieh ,  Chien-Ping Hung ,  Chi-Kang Chang ,  Shih-Chi Fu ,  Kuei-Shun Chen

IPC: H01L29/66 ,  H01L29/78

Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

公开(公告)号：US12125839B2

公开(公告)日：2024-10-22

申请号：US17107311

申请日：2020-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-I Huang ,  Ting-Wei Chiang ,  Shih-Chi Fu ,  Sheng-Fang Cheng ,  Jung-Chan Yang

IPC: H01L27/02 ,  G06F30/39 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0207 ,  G06F30/39 ,  H01L27/0886 ,  H01L29/66545 ,  H01L21/823431

Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

公开(公告)号：US10854593B2

公开(公告)日：2020-12-01

申请号：US16206746

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-I Huang ,  Ting-Wei Chiang ,  Shih-Chi Fu ,  Sheng-Fang Cheng ,  Jung-Chan Yang

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/66 ,  G06F30/39 ,  H01L21/8234

Abstract: A method includes the operations below. A first and second layout patterns corresponding to a first and second area are placed. Third layout patterns corresponding to a first continuous fin over the first area and second area, and corresponding to a second fin including separate portions spaced apart by a first recess over the first area are placed. A fourth layout pattern, corresponding to a dummy gate, at the recess portion and between the first layout pattern and the second layout pattern, is placed to generate a layout design of a semiconductor device. A side of the second area facing the first recess is substantially flat, and the semiconductor device is fabricated by a tool based on the layout design. A first length of the first continuous fin is equal to a sum of a second length of the second fin and a third length of the first recess.