公开(公告)号：US20210118805A1

公开(公告)日：2021-04-22

申请号：US16656715

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Cheng-Chi CHUANG ,  Chia-Tien WU ,  Jiann-Tyng TZENG ,  Shih-Wei PENG ,  Wei-Cheng LIN

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

公开(公告)号：US20180151729A1

公开(公告)日：2018-05-31

申请号：US15471318

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Charles Chew-Yuen YOUNG ,  Yi-Ming SHEU ,  Chun-Fu CHENG ,  Yi-Han WANG

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure also includes a gate stack structure in the dielectric layer. The semiconductor device structure further includes a semiconductor wire partially surrounded by the gate stack structure. In addition, the semiconductor device structure includes a contact electrode in the dielectric layer and electrically connected to the semiconductor wire. The contact electrode and the gate stack structure extend from the semiconductor wire in opposite directions.

公开(公告)号：US20160268244A1

公开(公告)日：2016-09-15

申请号：US15159692

申请日：2016-05-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  H01L23/535 ,  G06F17/50 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure includes following operations. Gate structures are arranged above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure. The first and second active regions are spaced apart by the non-active region. Contacts are arranged above the first and second active regions. At least one gate via is arranged above the first active region or the second active region. The at least one gate via is electrically coupled with the gate structures. At least one local interconnect is selectively arranged over the non-active region, to couple at least one of the contacts above the first active region to at least one of the contacts above the second active region.

Abstract translation: 一种形成半导体结构的方法包括以下操作。 栅极结构布置在半导体结构的衬底的第一有源区，第二有源区和非有源区的上方。 第一和第二有源区域被非有源区域隔开。 触点设置在第一和第二活动区域的上方。 至少一个栅极通孔布置在第一有源区或第二有源区的上方。 至少一个栅极通孔与栅极结构电耦合。 至少一个局部互连选择性地布置在非有源区上方，以将第一有源区上方的至少一个触点耦合到第二有源区上方的至少一个触点。

公开(公告)号：US20160064322A1

公开(公告)日：2016-03-03

申请号：US14476349

申请日：2014-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Yung-Sung YEN ,  Kam-Tou SIO ,  Tsong-Hua OU ,  Chun-Kuang CHEN ,  Ru-Gun LIU ,  Shu-Hui SUNG ,  Charles Chew-Yuen YOUNG

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/118

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: 0.2   P gate   min + 0.35   L gate   min + 0.3   H gate   min - 20 0.2   L gate   min + 0.8   H gate   min - 5 × 0.3   L gate   min + 0.3   H gate   min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures. Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.

Abstract translation: 提供半导体结构。 半导体结构包括沿着形成在衬底上的第一方向延伸的多个栅极结构以及与衬底上的栅极结构相邻形成的触点。 半导体结构还包括形成在栅极结构上的多个金属层。 此外，一些金属层包括在第一方向上延伸的金属线，并且一些金属层包括沿基本上垂直于第一方向的第二方向延伸的金属线。 此外，栅极结构遵循以下公式：0.2P门min + 0.35min min min H门槛最小 - 5×0.3L门min + 0.3H门min + 5 38≤0.32 P门min是门结构的栅间距中的最小值。 Lgate min是门结构的栅极长度之间的最小值。 Hgate min是门结构栅极高度的最小值。