公开(公告)号：US20200098923A1

公开(公告)日：2020-03-26

申请号：US16696845

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

公开(公告)号：US20140103438A1

公开(公告)日：2014-04-17

申请号：US14108391

申请日：2013-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching WANG ,  Jon-Hsu HO ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L29/78

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.

Abstract translation: 一种多栅半导体器件及其制造方法。 形成多栅半导体器件，其包括形成在具有第一掺杂剂类型的半导体衬底上的第一晶体管的第一鳍。 第一晶体管具有第一掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一掺杂剂型半导体衬底上的第二晶体管的第二鳍。 第二晶体管具有第二掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一鳍片的沟道区域上的第二掺杂剂类型的栅极电极层和形成在第二鳍片的沟道区域上的第一掺杂剂类型的栅极电极层。

公开(公告)号：US20180301560A1

公开(公告)日：2018-10-18

申请号：US16016748

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

公开(公告)号：US20150162334A1

公开(公告)日：2015-06-11

申请号：US14624782

申请日：2015-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jon-Hsu HO ,  Chih-Ching WANG ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Chih-Chieh YEH ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract translation: 形成包括半导体衬底的多栅极半导体器件。 多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。 第一晶体管具有形成在其中的第一沟道区。 第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。 第二浓度高于第一浓度。 第一晶体管还包括形成在第一沟道区上的第一栅电极层。 第一栅极电极层可以是第二掺杂剂类型。 第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。 第二沟道区域部分可以形成在第一沟道区域部分上。

公开(公告)号：US20180151729A1

公开(公告)日：2018-05-31

申请号：US15471318

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Charles Chew-Yuen YOUNG ,  Yi-Ming SHEU ,  Chun-Fu CHENG ,  Yi-Han WANG

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure also includes a gate stack structure in the dielectric layer. The semiconductor device structure further includes a semiconductor wire partially surrounded by the gate stack structure. In addition, the semiconductor device structure includes a contact electrode in the dielectric layer and electrically connected to the semiconductor wire. The contact electrode and the gate stack structure extend from the semiconductor wire in opposite directions.

公开(公告)号：US20180145176A1

公开(公告)日：2018-05-24

申请号：US15355844

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.

公开(公告)号：US20220359754A1

公开(公告)日：2022-11-10

申请号：US17812997

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.