Resistive Memory Array
    21.
    发明申请
    Resistive Memory Array 有权
    电阻式存储器阵列

    公开(公告)号:US20150269997A1

    公开(公告)日:2015-09-24

    申请号:US14219350

    申请日:2014-03-19

    Abstract: A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line.

    Abstract translation: 公开了一种包括电流源模块,电流吸收模块和存储体的电路。 电流源模块,电流模块和存储器组中的每一个都连接到第一位/源极线和第二位/源极线。 存储体由当前的源模块和当前的模块组成。 当电流源模块和电流接收模块从第一位/源线接收到触发脉冲和具有第一状态的选择信号时,电流源模块被激活以产生到第一位/源线的工作电流, 通过存储体的传导存储单元并且激活电流吸收模块以从第二位/源极线中漏去工作电流。

    Adaptive word-line boost driver
    22.
    发明授权
    Adaptive word-line boost driver 有权
    自适应字线升压驱动

    公开(公告)号:US08908439B2

    公开(公告)日:2014-12-09

    申请号:US13706380

    申请日:2012-12-06

    CPC classification number: G11C16/08 G11C8/08 G11C11/4085 G11C16/06

    Abstract: A word line driver circuit includes a first transistor having its gate coupled to a first node configured to receive a word line select signal. A second transistor has its gate coupled to the first node and a drain coupled to a drain of the first transistor at a second node that is coupled to a word line. A word line assist control circuit is coupled to the first node, to the word line, and to a gate of a third transistor. The word line assist control circuit is configured to turn on or turn off the third transistor to adjust a voltage of the word line.

    Abstract translation: 字线驱动器电路包括第一晶体管,其第一晶体管的栅极耦合到被配置为接收字线选择信号的第一节点。 第二晶体管具有耦合到第一节点的栅极,以及耦合到字线的第二节点处耦合到第一晶体管的漏极的漏极。 字线辅助控制电路耦合到第一节点,字线和第三晶体管的栅极。 字线辅助控制电路被配置为接通或关断第三晶体管以调节字线的电压。

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