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    Method and apparatus for MRAM sense reference trimming
    1.
    发明授权
    Method and apparatus for MRAM sense reference trimming 有权

    公开(公告)号：US09406367B2

    公开(公告)日：2016-08-02

    申请号：US14868425

    申请日：2015-09-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yue-Der Chih ,  Kai-Chun Lin ,  Hung-Chang Yu

    IPC: G11C11/00 ,  G11C11/16 ,  G11C7/14 ,  G11C29/02

    CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/1675 ,  G11C29/021 ,  G11C29/028

    Abstract: A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current.

    MRAM SMART BIT WRITE ALGORITHM WITH ERROR CORRECTION PARITY BITS
    2.
    发明申请
    MRAM SMART BIT WRITE ALGORITHM WITH ERROR CORRECTION PARITY BITS 有权
    具有错误校正奇偶校验位的MRAM SMART BIT写入算法

    公开(公告)号：US20150355963A1

    公开(公告)日：2015-12-10

    申请号：US14827591

    申请日：2015-08-17

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Yue-Der Chih ,  Hung-Chang Yu ,  Kai-Chun Lin ,  Chin-Yi Huang ,  Laun C. Tran

    IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

    CPC classification number: G06F11/1056 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1052 ,  G06F11/1402 ,  G06F11/141 ,  G11C11/1675 ,  G11C11/1677 ,  G11C2013/0076 ,  H03M13/11 ,  H03M13/611

    Abstract: Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.

    Abstract translation: 一些实施例涉及包括写入电路，读取电路和比较电路的系统。 写电路被配置为尝试将期望的多位字写入存储器件中的存储器位置。 读取电路被配置为从存储器位置读取实际的多位字。 比较电路被配置为将从存储器位置读取的实际多位字与预先写入存储器位置的预期多位字进行比较，以区分实际多位字中的多个错误位和 实际多位字中正确位数。 写电路还被配置为将错误位的数量重写到存储器位置，而不尝试将正确位的数量重写到存储器位置。

    Accommodating balance of bit line and source line resistances in magnetoresistive random access memory
    3.
    发明授权
    Accommodating balance of bit line and source line resistances in magnetoresistive random access memory 有权
    适应磁阻随机存取存储器中位线和源极线电阻的平衡

    公开(公告)号：US08923040B2

    公开(公告)日：2014-12-30

    申请号：US13753569

    申请日：2013-01-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kai-Chun Lin ,  Hung-Chang Yu ,  Ku-Feng Lin ,  Yue-Der Chih

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C7/12 ,  G11C7/14 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

    Abstract: A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances.

    Abstract translation: 存储器具有在不同逻辑状态下具有不同电阻的磁性隧道结元件，对于通过字线信号访问的位线信号中的位位置，该位线信号将寻址字中的每个位单元耦合在该位位置的位线和源极线之间。 位线和源极线在不同的字线位置越来越短，从而产生电阻体效应。 当读取电流时，钳位晶体管将位线耦合到感测电路，通过位单元施加电流，并将由感测电路比较的读取电压产生为诸如具有类似结构的参考位单元电路的可比电压的参考。 驱动控制通过例如字线地址改变作为字线位置的函数的开关晶体管的输入，以偏移不同的位和源极线电阻。

    Resistive memory array
    6.
    发明授权
    Resistive memory array 有权
    电阻式存储器阵列

    公开(公告)号：US09330746B2

    公开(公告)日：2016-05-03

    申请号：US14219350

    申请日：2014-03-19

    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

    Inventor： Kai-Chun Lin ,  Hung-Chang Yu ,  Ku-Feng Lin ,  Yue-Der Chih

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C11/1655 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1697 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/79 ,  G11C2213/82

    Abstract: A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line.

    Abstract translation: 公开了一种包括电流源模块，电流吸收模块和存储体的电路。 电流源模块，电流模块和存储器组中的每一个都连接到第一位/源极线和第二位/源极线。 存储体由当前的源模块和当前的模块组成。 当电流源模块和电流接收模块从第一位/源线接收到触发脉冲和具有第一状态的选择信号时，电流源模块被激活以产生到第一位/源线的工作电流， 通过存储体的传导存储单元并且激活电流吸收模块以从第二位/源极线中漏去工作电流。

    Resistive Memory Array
    8.
    发明申请
    Resistive Memory Array 有权
    电阻式存储器阵列

    公开(公告)号：US20150269997A1

    公开(公告)日：2015-09-24

    申请号：US14219350

    申请日：2014-03-19

    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

    Inventor： Kai-Chun Lin ,  Hung-Chang Yu ,  Ku-Feng Lin ,  Yue-Der Chih

    IPC: G11C13/00

    CPC classification number: G11C11/1655 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1697 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/79 ,  G11C2213/82

    Abstract: A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line.

    Abstract translation: 公开了一种包括电流源模块，电流吸收模块和存储体的电路。 电流源模块，电流模块和存储器组中的每一个都连接到第一位/源极线和第二位/源极线。 存储体由当前的源模块和当前的模块组成。 当电流源模块和电流接收模块从第一位/源线接收到触发脉冲和具有第一状态的选择信号时，电流源模块被激活以产生到第一位/源线的工作电流， 通过存储体的传导存储单元并且激活电流吸收模块以从第二位/源极线中漏去工作电流。

    Adaptive word-line boost driver
    10.
    发明授权
    Adaptive word-line boost driver 有权
    自适应字线升压驱动

    公开(公告)号：US08908439B2

    公开(公告)日：2014-12-09

    申请号：US13706380

    申请日：2012-12-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng Lin ,  Hung-Chang Yu ,  Kai-Chun Lin

    IPC: G11C8/08 ,  G11C16/08 ,  G11C16/06 ,  G11C11/408

    CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C11/4085 ,  G11C16/06

    Abstract: A word line driver circuit includes a first transistor having its gate coupled to a first node configured to receive a word line select signal. A second transistor has its gate coupled to the first node and a drain coupled to a drain of the first transistor at a second node that is coupled to a word line. A word line assist control circuit is coupled to the first node, to the word line, and to a gate of a third transistor. The word line assist control circuit is configured to turn on or turn off the third transistor to adjust a voltage of the word line.

    Abstract translation: 字线驱动器电路包括第一晶体管，其第一晶体管的栅极耦合到被配置为接收字线选择信号的第一节点。 第二晶体管具有耦合到第一节点的栅极，以及耦合到字线的第二节点处耦合到第一晶体管的漏极的漏极。 字线辅助控制电路耦合到第一节点，字线和第三晶体管的栅极。 字线辅助控制电路被配置为接通或关断第三晶体管以调节字线的电压。

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