利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

42 条记录 (耗时 0.021 秒)

    Bulk Semiconductor Substrate Configured to Exhibit Semiconductor-on-Insulator Behavior
    21.
    发明申请
    Bulk Semiconductor Substrate Configured to Exhibit Semiconductor-on-Insulator Behavior 审中-公开

    公开(公告)号：US20200006386A1

    公开(公告)日：2020-01-02

    申请号：US16118098

    申请日：2018-08-30

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Gulbagh Singh ,  Kun-Tsang Chuang ,  Hsin-Chi Chen

    IPC分类号： H01L27/12 ,  H01L29/10 ,  H01L29/06 ,  H01L21/84 ,  H01L21/762 ,  H01L21/265

    摘要： Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.

    Method of testing wafer
    26.
    发明授权
    Method of testing wafer 有权

    公开(公告)号：US11430733B2

    公开(公告)日：2022-08-30

    申请号：US17078523

    申请日：2020-10-23

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Yen-Hsung Ho ,  Chia-Yi Tseng ,  Chih-Hsun Lin ,  Kun-Tsang Chuang ,  Yung-Lung Hsu

    IPC分类号： H01L21/66 ,  H01L23/528 ,  H01L23/544 ,  H01L29/40 ,  H01L23/522

    摘要： A method includes capturing an image of a wafer, the wafer comprising a first conductive contact over an active region of the wafer and a second conductive contact over a shallow trench isolation (STI) region abutting the active region; identifying a brightness of a first contact region in the captured image at which the first conductive contact is rendered; identifying a brightness of a second contact region in the captured image at which the second conductive contact is rendered; and in response to the identified brightness of the first contact region in the captured image being substantially the same as the identified brightness of the second contact region in the captured image, determining that the second conductive contact is shorted to the first conductive contact.

    Isolation regions for reduced junction leakage
    27.
    发明授权
    Isolation regions for reduced junction leakage 有权

    公开(公告)号：US11264456B2

    公开(公告)日：2022-03-01

    申请号：US16855914

    申请日：2020-04-22

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Gulbagh Singh ,  Hsin-Chi Chen ,  Kun-Tsang Chuang

    IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/02 ,  H01L21/768

    摘要： The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.

    Shallow trench isolation for integrated circuits
    30.
    发明授权
    Shallow trench isolation for integrated circuits 有权

    公开(公告)号：US10522390B1

    公开(公告)日：2019-12-31

    申请号：US16014103

    申请日：2018-06-21

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Gulbagh Singh ,  Hsin-Chi Chen ,  Kun-Tsang Chuang

    IPC分类号： H01L29/76 ,  H01L21/762 ,  H01L27/12

    摘要： The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.