公开(公告)号：US10475897B2

公开(公告)日：2019-11-12

申请号：US15834757

申请日：2017-12-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark Van Dal ,  Matthias Passlack ,  Martin Christopher Holland

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/764 ,  H01L29/78

Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby foaming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.

公开(公告)号：US11728418B2

公开(公告)日：2023-08-15

申请号：US17735985

申请日：2022-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/775 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/205 ,  H01L29/66462

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US11411103B2

公开(公告)日：2022-08-09

申请号：US15930285

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US11257818B2

公开(公告)日：2022-02-22

申请号：US16353664

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Gerben Doornbos ,  Peter Ramvall

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/308 ,  H01L29/20 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

公开(公告)号：US20210225647A1

公开(公告)日：2021-07-22

申请号：US17224981

申请日：2021-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US10991576B2

公开(公告)日：2021-04-27

申请号：US16585571

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US10923581B2

公开(公告)日：2021-02-16

申请号：US16695650

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Peter Ramvall ,  Matthias Passlack ,  Carlos H. Diaz

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor structure including forming a first type semiconductor layer. The method also includes forming a semiconductor interlayer over the first type semiconductor layer. The method further includes forming a second type semiconductor layer over the semiconductor interlayer. The method further includes etching the first type semiconductor layer, the semiconductor interlayer, and the second type semiconductor layer to form a fin structure. The method further includes oxidizing the semiconductor interlayer.

公开(公告)号：US20210043839A1

公开(公告)日：2021-02-11

申请号：US17068736

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Marcus Johannes Henricus Van Dal ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L51/00 ,  C23C16/455 ,  C23C16/56 ,  H01L23/544

Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.

公开(公告)号：US10672899B2

公开(公告)日：2020-06-02

申请号：US16194140

申请日：2018-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US20190355818A1

公开(公告)日：2019-11-21

申请号：US15983998

申请日：2018-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peter Ramvall ,  Matthias Passlack

IPC: H01L29/12 ,  H01L29/20 ,  H01L29/15 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.