公开(公告)号：US20200058649A1

公开(公告)日：2020-02-20

申请号：US16103721

申请日：2018-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device has a first fin, a second fin, an isolation structure between the first fin and the second fin, a dielectric stage in the isolation structure, and a helmet layer over the dielectric stage. A top surface of the helmet layer is higher than a top surface of the isolation structure.

公开(公告)号：US20190035912A1

公开(公告)日：2019-01-31

申请号：US15663089

申请日：2017-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes active gate stacks over the fin structure. The semiconductor device structure further includes a dummy gate stack over the fin structure. The dummy gate stack is between the active gate stacks. In addition, the semiconductor device structure includes spacer elements over sidewalls of the dummy gate stack and the active gate stacks. The semiconductor device structure also includes an isolation feature below the dummy gate stack, the active gate stacks and the spacer elements. The isolation feature extends into the fin structure from the bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure.

公开(公告)号：US20190006486A1

公开(公告)日：2019-01-03

申请号：US15635337

申请日：2017-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.

公开(公告)号：US20220068919A1

公开(公告)日：2022-03-03

申请号：US17007742

申请日：2020-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.

公开(公告)号：US20210265485A1

公开(公告)日：2021-08-26

申请号：US17314763

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first dielectric fin, a semiconductor fin, a metal gate structure, an epitaxy structure, and a contact etch stop layer. The first dielectric fin is disposed over the substrate. The semiconductor fin is disposed over the substrate, in which along a lengthwise direction of the first dielectric fin and the semiconductor fin, the first dielectric fin is in contact with a first sidewall of the semiconductor fin. The metal gate structure crosses the first dielectric fin and the semiconductor fin. The epitaxy structure is over and in contact with the semiconductor fin. The contact etch stop layer is over and in contact with first dielectric fin.

公开(公告)号：US20210135008A1

公开(公告)日：2021-05-06

申请号：US16834264

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Guan-Lin CHEN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the stressor structure.

公开(公告)号：US20210134795A1

公开(公告)日：2021-05-06

申请号：US16871740

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. Each of the first epitaxial structure and the second epitaxial structure extends exceeding a top surface of the semiconductor fin. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure further extends exceeding opposite sidewalls of the first epitaxial structure.

公开(公告)号：US20200343377A1

公开(公告)日：2020-10-29

申请号：US16683559

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure over a substrate, a first dielectric layer adjacent to the fin structure, and a second dielectric layer covering a sidewall of the first dielectric layer. The first dielectric layer has a different etching selectivity than the second dielectric layer. A bottom portion of the second dielectric layer is lower than a bottom surface of the first dielectric layer. The semiconductor device structure also includes a source/drain feature over the fin structure and covering a sidewall of the second dielectric layer, nanostructures over the fin structure, and a gate stack wrapping around the nanostructures

公开(公告)号：US20200343376A1

公开(公告)日：2020-10-29

申请号：US16395731

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a dielectric fin structure over the substrate. The semiconductor device structure also includes a semiconductor fin structure adjacent to the dielectric fin structure. The semiconductor device structure also includes a metal gate stack across the dielectric fin structure and the semiconductor fin structure. The semiconductor device structure also includes a source/drain feature over the semiconductor fin structure. The semiconductor device structure also includes a source/drain spacer interposed between the source/drain feature and the dielectric fin structure.

公开(公告)号：US20190139777A1

公开(公告)日：2019-05-09

申请号：US16221766

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Wen-Ting LAN ,  Shi-Ning JU ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.