公开(公告)号：US20190139777A1

公开(公告)日：2019-05-09

申请号：US16221766

申请日：2018-12-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Wen-Ting LAN ,  Shi-Ning JU ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/823431 ,  H01L29/66795

摘要： A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.

公开(公告)号：US20240063288A1

公开(公告)日：2024-02-22

申请号：US18501554

申请日：2023-11-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Chen LO ,  Jung-Hao CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC分类号： H01L29/51 ,  H01J37/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/517 ,  H01J37/00 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/4966

摘要： A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

公开(公告)号：US20240021710A1

公开(公告)日：2024-01-18

申请号：US18360427

申请日：2023-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jung-Hao CHANG ,  Li-Te LIN

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/401 ,  H01L21/31116 ,  H01L21/32136

摘要： A method includes forming a gate structure across a channel region from a top view, the gate structure comprising a work function metal and a gate dielectric layer wrapping around the work function metal, the gate dielectric layer having a U-shaped cross-sectional profile; performing a first plasma etching process, by using a chlorine-containing reactant, on the gate structure; performing a second plasma etching process, by using a bromine-containing, reactant on the gate structure.

公开(公告)号：US20200287047A1

公开(公告)日：2020-09-10

申请号：US16880864

申请日：2020-05-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092

摘要： A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

公开(公告)号：US20190097056A1

公开(公告)日：2019-03-28

申请号：US16141509

申请日：2018-09-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L21/84 ,  H01L21/306 ,  H01L21/02 ,  H01L27/12

摘要： A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

公开(公告)号：US20220336623A1

公开(公告)日：2022-10-20

申请号：US17856892

申请日：2022-07-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Chen LO ,  Jung-Hao CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC分类号： H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01J37/00 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3213

摘要： A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

公开(公告)号：US20210384325A1

公开(公告)日：2021-12-09

申请号：US17411704

申请日：2021-08-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jung-Hao CHANG ,  Li-Te LIN

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/311 ,  H01L21/3213

摘要： A semiconductor device includes a substrate, a semiconductor fin, gate spacers, a gate structure. The semiconductor fin is on the substrate. The gate spacers are over the semiconductor fin. The gate structure is on the semiconductor fin and between the gate spacers. The gate structure includes a gate dielectric layer and a first work function metal over the gate dielectric layer, in which a top surface of the first work function metal is lower than a top surface of the gate dielectric layer, and a distance between the top surface of the first work function metal and the top surface of the gate dielectric layer is less than about 1 nm.

公开(公告)号：US20210226057A1

公开(公告)日：2021-07-22

申请号：US16744480

申请日：2020-01-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Hung CHU ,  Sung-Li WANG ,  Fang-Wei LEE ,  Jung-Hao CHANG ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/311 ,  H01L29/417

摘要： A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.

公开(公告)号：US20240313116A1

公开(公告)日：2024-09-19

申请号：US18670123

申请日：2024-05-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L21/02532 ,  H01L21/0262 ,  H01L2029/7858

摘要： A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

公开(公告)号：US20230089130A1

公开(公告)日：2023-03-23

申请号：US18070285

申请日：2022-11-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092

摘要： A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.