公开(公告)号：US11699739B2

公开(公告)日：2023-07-11

申请号：US17586083

申请日：2022-01-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY ,  NATIONAL TAIWAN NORMAL UNIVERSITY

Inventor： Tung-Ying Lee ,  Tse-An Chen ,  Tzu-Chung Wang ,  Miin-Jang Chen ,  Yu-Tung Yin ,  Meng-Chien Yang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/6653 ,  H01L21/02603 ,  H01L21/28141 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.

公开(公告)号：US11688605B2

公开(公告)日：2023-06-27

申请号：US17078247

申请日：2020-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tse-An Chen ,  Lain-Jong Li

IPC: H01L21/18 ,  H01L21/02 ,  H01L21/683 ,  H01L29/66 ,  H01L29/20 ,  H01L29/24 ,  H01L29/76 ,  H01L21/78

CPC classification number: H01L21/187 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/6835 ,  H01L21/7813 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66462 ,  H01L29/7606 ,  H01L2221/68368

Abstract: The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.

公开(公告)号：US11508572B2

公开(公告)日：2022-11-22

申请号：US16837580

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chun-Yi Chou ,  Po-Hsien Cheng ,  Tse-An Chen ,  Miin-Jang Chen

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.

公开(公告)号：US11244866B2

公开(公告)日：2022-02-08

申请号：US16932268

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Lain-Jong Li ,  Tzu-Chiang Chen

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/306 ,  H01L21/28 ,  H01L29/06 ,  H01L21/02 ,  B82Y40/00

Abstract: In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.

公开(公告)号：US20210376133A1

公开(公告)日：2021-12-02

申请号：US16887729

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66

Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.