公开(公告)号：US20220359406A1

公开(公告)日：2022-11-10

申请号：US17869286

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chun-Chih Chuang ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Jiun Yi Wu

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

公开(公告)号：US20220020655A1

公开(公告)日：2022-01-20

申请号：US16933910

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Wei Cheng ,  Jiun-Yi Wu ,  Hsin-Yu Pan ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/40

Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

公开(公告)号：US20210384120A1

公开(公告)日：2021-12-09

申请号：US17408840

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shi Liu ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Jung Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Li-Wei Chou

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L21/683 ,  H01L23/498

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

公开(公告)号：US20210202266A1

公开(公告)日：2021-07-01

申请号：US16869066

申请日：2020-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US20210098325A1

公开(公告)日：2021-04-01

申请号：US16746976

申请日：2020-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chien-Hsun Lee ,  Jung-Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang

IPC: H01L23/31 ,  H01L23/522

Abstract: A semiconductor package including a first semiconductor device, a second semiconductor device, an insulating encapsulant, a redistribution structure and a supporting element is provided. The insulating encapsulant encapsulates the first semiconductor device and the second semiconductor device. The redistribution structure is over the first semiconductor device, the second semiconductor device and the insulating encapsulant. The redistribution structure is electrically connected to the first semiconductor device and the second semiconductor device. The supporting element is embedded in one of the insulating encapsulant and the redistribution structure.

公开(公告)号：US20200328173A1

公开(公告)日：2020-10-15

申请号：US16914478

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hai-Ming Chen ,  Kuan-Lin Ho ,  Yu-Min Liang

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L21/683

Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

公开(公告)号：US20200043819A1

公开(公告)日：2020-02-06

申请号：US16171326

申请日：2018-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chien-Hsun Lee ,  Yu-Min Liang

IPC: H01L23/24 ,  H01L25/065 ,  H01L23/00 ,  H01L23/433 ,  H01L23/31

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure.

公开(公告)号：US20190148340A1

公开(公告)日：2019-05-16

申请号：US15835466

申请日：2017-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Chien-Hsun Lee ,  Kuan-Lin Ho ,  Yu-Min Liang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a plurality of conductive terminals. The first encapsulant is at least disposed between the first die and the second die, and on the second die. The second encapsulant is aside the first die and the second die. The conductive terminals are electrically connected to the first die and the second die through a redistribution layer (RDL) structure. An interface is existed between the first encapsulant and the second encapsulant.

公开(公告)号：US10276508B2

公开(公告)日：2019-04-30

申请号：US15719493

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Lin Ho ,  Chin-Liang Chen ,  Chi-Yang Yu ,  Yu-Min Liang

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/367

Abstract: Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a plurality of chips, a first molding compound, a first redistribution structure, a second molding compound and a second redistribution structure. The first molding compound encapsulates the chips. The first redistribution structure is disposed over the plurality of chips and the first molding compound. The second molding compound surrounds the first molding compound. The second redistribution structure is disposed over the first redistribution structure, the first molding compound and the second molding compound.

公开(公告)号：US10157871B1

公开(公告)日：2018-12-18

申请号：US15730760

申请日：2017-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hai-Ming Chen ,  Kuan-Lin Ho ,  Yu-Min Liang

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a plurality of conductive pillars, a seed layer, and a plurality of conductive bumps. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die and includes a plurality of dielectric layers that are sequentially stacked and a plurality of conductive patterns sandwiched between the dielectric layers. A Young's modulus of the dielectric layer farthest away from the die is higher than a Young's modulus of each of the rest of the dielectric layers. The conductive patterns are electrically connected to each other. The conductive pillars are disposed on and electrically connected to the redistribution structure. The seed layer is located between the conductive pillars and the redistribution structure. The conductive bumps are disposed on the plurality of conductive pillars.