公开(公告)号：US20190096816A1

公开(公告)日：2019-03-28

申请号：US15719493

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Lin Ho ,  Chin-Liang Chen ,  Chi-Yang Yu ,  Yu-Min Liang

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

Abstract: Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a plurality of chips, a first molding compound, a first redistribution structure, a second molding compound and a second redistribution structure. The first molding compound encapsulates the chips. The first redistribution structure is disposed over the plurality of chips and the first molding compound. The second molding compound surrounds the first molding compound. The second redistribution structure is disposed over the first redistribution structure, the first molding compound and the second molding compound.

公开(公告)号：US09287233B2

公开(公告)日：2016-03-15

申请号：US14093856

申请日：2013-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Liang Chen ,  Wei-Ting Lin ,  Kuan-Lin Ho ,  Yu-Chih Liu ,  Chun-Cheng Lin ,  Shih-Yen Lin

IPC: H01L23/12 ,  H01L23/34 ,  H01L23/10 ,  H01L23/00 ,  H01L23/42 ,  H01L23/367

CPC classification number: H01L24/81 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83455 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/164 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L21/563

Abstract: The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.

Abstract translation: 本公开涉及具有多个不同粘合剂层的集成芯片封装，其提供用于衬底和/或IC芯片的低盖诱导应力良好翘曲控制以及相关联的形成方法。 集成芯片封装具有通过导电互连结构耦合到下面的衬底的集成芯片（IC）裸芯片。 具有第一杨氏模量的第一粘合剂层在围绕IC管芯的第一多个位置处设置在基板上。 具有不同于第一杨氏模量的第二杨氏模量的第二粘合层在围绕IC管芯的第二多个位置处设置在基板上。 盖通过第一和第二粘合剂层固定到基底上，并延伸到覆盖IC芯片的位置。

公开(公告)号：US20150155221A1

公开(公告)日：2015-06-04

申请号：US14093856

申请日：2013-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Liang Chen ,  Wei-Ting Lin ,  Kuan-Lin Ho ,  Yu-Chih Liu ,  Chun-Cheng Lin ,  Shih-Yen Lin

IPC: H01L23/433 ,  H01L23/00 ,  H01L23/16 ,  H01L23/02 ,  H01L21/52 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83455 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/164 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L21/563

Abstract: The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.

Abstract translation: 本公开涉及具有多个不同粘合剂层的集成芯片封装，其提供用于衬底和/或IC芯片的低盖诱导应力良好翘曲控制以及相关联的形成方法。 集成芯片封装具有通过导电互连结构耦合到下面的衬底的集成芯片（IC）裸芯片。 具有第一杨氏模量的第一粘合剂层在围绕IC管芯的第一多个位置处设置在基板上。 具有不同于第一杨氏模量的第二杨氏模量的第二粘合层在围绕IC管芯的第二多个位置处设置在基板上。 盖通过第一和第二粘合剂层固定到基底上，并延伸到覆盖IC芯片的位置。

公开(公告)号：US11894312B2

公开(公告)日：2024-02-06

申请号：US17869286

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chun-Chih Chuang ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Jiun Yi Wu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19106

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

公开(公告)号：US10700031B2

公开(公告)日：2020-06-30

申请号：US16215679

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hai-Ming Chen ,  Kuan-Lin Ho ,  Yu-Min Liang

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L21/683

Abstract: An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure includes dielectric layers and conductive patterns. The dielectric layers are sequentially stacked and the conductive patterns are sandwiched between the dielectric layers. The seed layer and the conductive pillars are sequentially stacked over the redistribution structure. The seed layer is directly in contact with the conductive patterns closest to the conductive pillars. The buffer layer is disposed over the redistribution structure. The dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars. A Young's modulus of the buffer layer is higher than a Young's modulus of each of the dielectric layers of the redistribution structure.

公开(公告)号：US10658263B2

公开(公告)日：2020-05-19

申请号：US15993615

申请日：2018-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Wen-Lin Chen

IPC: H01L23/34 ,  H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

公开(公告)号：US20190131262A1

公开(公告)日：2019-05-02

申请号：US16215679

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hai-Ming Chen ,  Kuan-Lin Ho ,  Yu-Min Liang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/532 ,  H01L23/522

Abstract: An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure includes dielectric layers and conductive patterns. The dielectric layers are sequentially stacked and the conductive patterns are sandwiched between the dielectric layers. The seed layer and the conductive pillars are sequentially stacked over the redistribution structure. The seed layer is directly in contact with the conductive patterns closest to the conductive pillars. The buffer layer is disposed over the redistribution structure. The dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars. A Young's modulus of the buffer layer is higher than a Young's modulus of each of the dielectric layers of the redistribution structure.

公开(公告)号：US11315862B2

公开(公告)日：2022-04-26

申请号：US16916046

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Lin Ho ,  Chin-Liang Chen ,  Jiun-Yi Wu ,  Chi-Yang Yu ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.

公开(公告)号：US20200279790A1

公开(公告)日：2020-09-03

申请号：US16874621

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Wen-Lin Chen

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

公开(公告)号：US20240136299A1

公开(公告)日：2024-04-25

申请号：US18401928

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chun-Chih Chuang ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Jiun Yi Wu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19106

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.