公开(公告)号：US4476420A

公开(公告)日：1984-10-09

申请号：US443471

申请日：1982-11-22

申请人： Teruo Asakawa

发明人： Teruo Asakawa

IPC分类号： G01D5/244 ,  G01D5/245 ,  G05B19/39 ,  G05D3/12 ,  G05B1/01

CPC分类号： G05B19/39 ,  G05D3/121

摘要： Positioning of a movable body can be achieved at a high resolution by making use of two position signals generated by a position detector, whose magnitudes are sinusoidal functions having different phases of the position of the movable body. On the basis of the two sinusoidal position signals, two bi-level digital position signals having different phase from each other are derived, and digital control for movement of the movable body is effected by making use of these two bi-level digital position signals until the movable body is brought into the proximity of a desired position. Thereafter, control is switched from the digital control to analog control for movement of the movable body, in which a position signal whose manitude is a sinusoidal function of the position of the movable body and has a zero-cross point at the desired position is used as a reference position signal. This reference position signal can be synthesized from the two position signals generated by the position detector by means of a simple signal synthesizer circuit according to the present invention. The signal synthesizer circuit comprises two multiplier type digital-analog converters, each of which is applied with a digital input signal and an analog input signal such as, for example, the above-mentioned sinusoidal position signal generated by the position detector and generates an analog output signal that is product including an algebraic sign of the digital input signal and the analog input signal, and an adder having the respective analog output signals of the two multiplier type digital-analog converters applied to its input. By appropriately selecting the digital values of the digital input signals, a desired reference position signal can be derived at the output of the adder.

摘要翻译： 可以通过利用由位置检测器产生的两个位置信号以高分辨率来实现移动体的定位，位置检测器的大小是具有不同移动体位置的正弦函数。 基于两个正弦位置信号，导出具有彼此不同相位的两个双电平数字位置信号，并且通过利用这两个双电平数字位置信号来实现移动体的移动的数字控制，直到 可移动体被带到所需位置附近。 此后，将控制从数字控制切换到可移动体的运动的模拟控制，其中使用其位置信号，其位置信号是可移动体的位置的正弦函数并且在期望位置处具有零交叉点 作为参考位置信号。 可以通过根据本发明的简单信号合成器电路由位置检测器产生的两个位置信号来合成该参考位置信号。 信号合成器电路包括两个乘法器型数模转换器，每个转换器应用数字输入信号和模拟输入信号，例如由位置检测器产生的上述正弦位置信号，并产生模拟 输出信号，其是包括数字输入信号和模拟输入信号的代数符号的乘积，以及加法器，其具有应用于其输入的两个乘法器型数模转换器的相应模拟输出信号。 通过适当地选择数字输入信号的数字值，可以在加法器的输出端导出期望的参考位置信号。

公开(公告)号：US07566665B2

公开(公告)日：2009-07-28

申请号：US11024199

申请日：2004-12-29

申请人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

发明人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

IPC分类号： H01L21/302

CPC分类号： H01L21/67225 ,  C23C14/56 ,  C23C16/54 ,  H01L21/0405 ,  H01L21/67161 ,  H01L21/67173

摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.

摘要翻译： 本发明提供了一种用于在半导体衬底上施加一系列工艺的半导体器件制造线，并且通过采用直径为6英寸（150±3mm：SEAJ规格）的半导体晶片或半导体衬底上形成集成电路， 较少用于半导体衬底。 该制造线包括符合相同规格的两条子线，这些子线中的每一条由包括成膜单元，图案曝光单元，蚀刻单元和测试单元的一系列处理单元组成。 在至少一个图案曝光单元和一个蚀刻单元中，可以执行0.3μm或更小的精细处理。

公开(公告)号：US20090016859A1

公开(公告)日：2009-01-15

申请号：US11666163

申请日：2005-10-25

申请人： Teruo Asakawa

发明人： Teruo Asakawa

IPC分类号： B65H1/00

CPC分类号： H01L21/67727 ,  H01L21/67736 ,  H01L21/67775

摘要： A carrying system 1 has a carrying path which is laid out in such a manner as to pass through the lower sides of loading table 11 and the like provided at the front face side of treating devices 10, 100, 200, and covered by a cover 5. As the carrying path is positioned below the loading tables, the occupying areas of the loading table 11 and the like and portions of the region of the carrying path are shared so that space saving is achieved, and the accessibility to the treating device 10, 100 or the like from the front side thereof is improved, thereby realizing a layout which facilitates maintenance. A loading surface 11d or the like of the loading table 11 is set to a height which allows a conventional overhead-type carrying system 2 and unmanned carrying vehicle 3 of a floor-type carrying system to load an object on the loading surface, thereby ensuring the co-existence with the other carrying systems.

摘要翻译： 携带系统1具有输送路径，其布置成穿过设置在处理装置10,100,200的前表面处的装载台11等的下侧，并被盖 当承载路径位于装载台下方时，承载台11等的占有区域和运送路径的区域的部分被共享，从而实现节省空间，并且可处理装置10 ，100等从前侧提高，从而实现有利于维护的布局。 装载台11的装载面11d等被设定为允许地板式承载系统的常规塔式运载系统2和无人运载车辆3在装载面上装载物体的高度，从而确保 与其他携带系统的共存。

公开(公告)号：US06841485B1

公开(公告)日：2005-01-11

申请号：US09958970

申请日：2000-04-11

申请人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

发明人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

IPC分类号： C23C14/56 ,  C23C16/54 ,  H01L21/00 ,  H01L21/04 ,  H01L21/302

CPC分类号： H01L21/67225 ,  C23C14/56 ,  C23C16/54 ,  H01L21/0405 ,  H01L21/67161 ,  H01L21/67173

摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.

摘要翻译： 本发明提供了一种用于在半导体衬底上施加一系列工艺的半导体器件制造线，并且通过采用直径为6英寸（150±3mm：SEAJ规格）的半导体晶片或半导体衬底上形成集成电路， 较少用于半导体衬底。 该制造线包括符合相同规格的两条子线，这些子线中的每一条由包括成膜单元，图案曝光单元，蚀刻单元和测试单元的一系列处理单元组成。 在至少一个图案曝光单元和一个蚀刻单元中，可以执行0.3μm或更小的精细处理。

公开(公告)号：US06802934B2

公开(公告)日：2004-10-12

申请号：US10378890

申请日：2003-03-05

申请人： Hiroaki Saeki ,  Keiichi Matsushima ,  Teruo Asakawa ,  Masaki Narushima

发明人： Hiroaki Saeki ,  Keiichi Matsushima ,  Teruo Asakawa ,  Masaki Narushima

IPC分类号： H01L2100

CPC分类号： H01L21/67766 ,  H01L21/67167 ,  H01L21/67201 ,  H01L21/67742 ,  H01L21/67745 ,  Y10S414/135 ,  Y10S414/136

摘要： Two load lock chambers 130 and 132 are arranged between a first transfer chamber 122 and a second transfer chamber 133. Each of the load lock chambers is capable of accommodating a single wafer W. The first transfer chamber 122 is provided with a first transfer unit 124 having two substrate holders 124a, 124b each capable of holding a single object to be processed, in order to transport the wafer W among a load port site 120, the first load lock chamber 130, the second load lock chamber 132 and a positioning unit 150. The second transfer chamber 133 is provided with a second transfer unit 156 having two substrate holders 156a, 156b each capable of holding the single object to be processed, in order to transport the wafer between the first load lock chamber 130, the second load lock chamber 132 and respective vacuum processing chambers 158 to 164. Since the volume of each load lock chamber can be minimized, it is possible to perform the prompt control of atmospheres in the load lock chambers. Additionally, it is possible to perform the delivery of the wafers promptly.

摘要翻译： 两个负载锁定室130和132设置在第一传送室122和第二传送室133之间。每个负载锁定室能够容纳单个晶片W.第一传送室122设置有第一传送单元124 具有能够保持单个待处理物体的两个基板保持件124a，124b，以便在载荷端口位置120，第一加载锁定室130，第二加载锁定室132和定位单元150之间输送晶片W 第二传送室133设置有第二传送单元156，第二传送单元156具有两个能够保持单个待处理物体的基板保持器156a，156b，以便在第一加载锁定室130，第二加载锁 室132和相应的真空处理室158至164.由于每个负载锁定室的体积可以最小化，因此可以对负载锁中的气氛进行即时控制 mbers。 此外，可以及时执行晶片的传送。

公开(公告)号：US5374147A

公开(公告)日：1994-12-20

申请号：US942841

申请日：1992-09-10

申请人： Tsutomu Hiroki ,  Teruo Asakawa

发明人： Tsutomu Hiroki ,  Teruo Asakawa

IPC分类号： B65G49/07 ,  H01L21/687 ,  B65G47/24

CPC分类号： H01L21/68707 ,  Y10S414/136

摘要： A device for transferring a LCD substrate under a reduced pressure atmosphere comprises a first stage on which the LCD substrate is mounted such that the surface of the LCD substrate is substantially horizontal, a multi-joint arm mechanism for mounting the LCD substrate on a second stage of a delivery position after moving the first stage in substantially horizontal plane, a mechanism for pushing the LCD substrate on the first and second stages, and for positioning the LCD substrate at a home position.

摘要翻译： 用于在减压气氛下转移LCD基板的装置包括：第一阶段，LCD基板被安装在其上，使得LCD基板的表面基本上水平;多关节臂机构，用于将LCD基板安装在第二台上 在基本水平的平面中移动第一级之后的输送位置，用于在第一和第二级上推动LCD基板并将LCD基板定位在原始位置的机构。

公开(公告)号：US5248886A

公开(公告)日：1993-09-28

申请号：US842421

申请日：1992-02-27

申请人： Teruo Asakawa ,  Tetsu Osawa ,  Noboru Hosaka

发明人： Teruo Asakawa ,  Tetsu Osawa ,  Noboru Hosaka

IPC分类号： B65G49/00 ,  C23C14/56 ,  C30B35/00 ,  H01J37/317 ,  H01L21/00 ,  H01L21/265 ,  H01L21/677

CPC分类号： H01L21/67069 ,  C30B35/005 ,  H01L21/67201 ,  H01L21/67213 ,  H01L21/67259 ,  H01L21/67745

摘要： Load lock chambers having a function of detecting positional deviation of wafers are provided in a process chamber of an ion injection apparatus, two on a carrying-in side, and two on a carrying-out side. One load lock chamber on the carrying-in side and one on the carrying-out side are used as a standby. Carrying-in carrying-out members and are outside of the process chamber. Two transfer members are in the process chamber. A dummy wafer stage is formed at a position which can be accessed by the transfer members. Wafers are transferred from load stages by the carrying-in member via the load lock chambers to the process chamber through a double operation line. Loading a wafer on the turn table and unloading a wafer therefrom can be performed simultaneously by operations of the transfer members and. The wafers are similarly carried out of the apparatus in a double operation line. At this time, dummy wafers in the process chamber can be used, if necessary.

公开(公告)号：US5064337A

公开(公告)日：1991-11-12

申请号：US552852

申请日：1990-07-12

申请人： Teruo Asakawa ,  Tetsu Ohsawa

发明人： Teruo Asakawa ,  Tetsu Ohsawa

IPC分类号： H01L21/677

CPC分类号： H01L21/67769 ,  Y10S414/14

摘要： A handling apparatus, used for handling a carrier of semiconductor wafers, comprises a first mechanism for transferring a carrier between a loader/unloader table and a storage compartment, and a second mechanism, for moving the first mechanism in both vertical and horizontal directions. The first mechanism includes an arm, a loading portion for loading the carrier, and an arm-rocking mechanism. The second mechanism moves the first mechanism to the loader/unloader table, picks up the carrier, and then moves the first mechanism to the storage compartment, where the arm is rocked, so as to discharge the object from the loading portion.

摘要翻译： 用于处理半导体晶片的载体的处理装置包括用于在装载机/卸载台和存储室之间传送载体的第一机构和用于在垂直和水平方向上移动第一机构的第二机构。 第一机构包括臂，用于装载托架的装载部分和臂摆动机构。 第二机构将第一机构移动到装载机/卸载机台，拾取载体，然后将第一机构移动到臂被摇动的储藏室，以将物体从装载部分排出。

公开(公告)号：US20050260824A1

公开(公告)日：2005-11-24

申请号：US11189700

申请日：2005-07-27

申请人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

发明人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

IPC分类号： C23C14/56 ,  C23C16/54 ,  H01L21/00 ,  H01L21/04 ,  H01L21/76

CPC分类号： H01L21/67225 ,  C23C14/56 ,  C23C16/54 ,  H01L21/0405 ,  H01L21/67161 ,  H01L21/67173

摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.

公开(公告)号：US06224679B1

公开(公告)日：2001-05-01

申请号：US09131280

申请日：1998-08-10

申请人： Yoshiaki Sasaki ,  Teruo Asakawa

发明人： Yoshiaki Sasaki ,  Teruo Asakawa

IPC分类号： C23C1600

CPC分类号： H01L21/67017 ,  B08B5/00 ,  H01L21/67772 ,  Y10S414/135

摘要： A wafer processing system comprises a container-housing chamber for housing the conveying container conveyed from the common area, a cleaning chamber disposed adjacent to the container-housing chamber, and a load-lock chamber disposed adjacent to the cleaning chamber. The cleaning chamber has an inlet line for introducing a clean gas into the cleaning chamber and a pressure control means for controlling the pressure in the cleaning chamber. The load-lock chamber has a conveying unit capable of extending to the container-housing chamber through the cleaning chamber, in order to take out the object from the conveying container housed in the container-housing chamber to the load-lock chamber through the cleaning chamber.

摘要翻译： 晶片处理系统包括用于容纳从公共区域输送的输送容器的容器容纳室，邻近容器容纳室设置的清洁室和邻近清洁室设置的装载锁定室。 清洁室具有用于将清洁气体引入清洁室的入口管线和用于控制清洁室中的压力的​​压力控制装置。 负载锁定室具有能够通过清洁室延伸到容器容纳室的输送单元，以便通过清洁将物体从容纳在容器容纳室中的输送容器取出到装载锁定室 房间。