公开(公告)号：US08445943B2

公开(公告)日：2013-05-21

申请号：US13010191

申请日：2011-01-20

申请人： Hiroshi Furuta

发明人： Hiroshi Furuta

IPC分类号： H01L29/72

CPC分类号： H01L27/0928 ,  H03K19/00338

摘要： A semiconductor integrated circuit device includes: a plurality of data holding circuits; and a plurality of wells. The plurality of data holding circuits is provided in a substrate of a first conductive type. Each of the plurality of data holding circuits includes a first well of the first conductive type and a second well of a second conductive type different from the first conductive type. The plurality of wells is arranged in two directions for the each of the plurality of data holding circuits.

摘要翻译： 一种半导体集成电路装置，包括：多个数据保持电路; 和多个井。 多个数据保持电路设置在第一导电类型的衬底中。 多个数据保持电路中的每一个包括第一导电类型的第一阱和不同于第一导电类型的第二导电类型的第二阱。 对于多个数据保持电路中的每一个，多个阱被布置在两个方向上。

公开(公告)号：US08310297B2

公开(公告)日：2012-11-13

申请号：US12929753

申请日：2011-02-14

申请人： Kenjyu Shimogawa ,  Hiroshi Furuta

发明人： Kenjyu Shimogawa ,  Hiroshi Furuta

IPC分类号： H03K3/01

CPC分类号： H03K5/05 ,  H01L2924/0002 ,  H03K3/0375 ,  H03K3/356156 ,  H03K2005/00058 ,  H01L2924/00

摘要： Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.

摘要翻译： 公开了一种半导体器件，包括：模式控制电路，当待机控制信号处于激活状态时，基于来自定时器电路的定时器输出信号，生成改变功能电路部分的逻辑状态的MODE控制输出信号 以及输出控制电路，其接收所述功能电路部的输出信号，并控制所述输出信号的输出; 基于通过延迟电路延迟MODE控制输出信号而产生的延迟输出信号。 当功能电路部分通过MODE控制输出信号改变逻辑状态时，输出控制电路不将功能电路部分输出信号传送到输出，而是在功能电路部分变化之前保持并输出功能电路部分输出信号 逻辑状态由MODE控制输出信号。

公开(公告)号：US08050108B2

公开(公告)日：2011-11-01

申请号：US12611589

申请日：2009-11-03

申请人： Kenjiyu Shimogawa ,  Hiroshi Furuta ,  Shunsaku Naga ,  Takayuki Shirai

发明人： Kenjiyu Shimogawa ,  Hiroshi Furuta ,  Shunsaku Naga ,  Takayuki Shirai

IPC分类号： G11C7/10

CPC分类号： G11C7/22 ,  G11C7/08 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005

摘要： Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit (24) is provided between each bit line (21) and each sense amplifier (26). In writeback, the switch circuits are turned on at staggered time points. In readout, the switch circuits are turned on to read memory cell data to the sense amplifiers while the sense amplifiers are turned off, and the switch circuits are then turned off once. After that, the sense amplifiers are turned on to amplify the read data. The switch circuits are subsequently divided into groups and turned on again to write back the data amplified by the sense amplifiers to the memory cells. The switch circuits are divided into groups to be turned on at staggered time points during the writeback, to thereby avoid concentration of the writeback current in one time period.

摘要翻译： 提供了能够避免在每个位线（21）和每个读出放大器（26）之间设置开关电路（24）的回写电流的集中的破坏性读出半导体存储器件。 在回写中，开关电路以交错的时间点接通。 在读出时，开关电路被接通以将读出放大器的存储单元数据读取到读出放大器，同时关闭读出放大器，然后关闭开关电路。 之后，读出放大器被打开以放大读取的数据。 开关电路随后被分成组并再次导通以将由读出放大器放大的数据写回存储单元。 开关电路被分成在写入期间以交错的时间点接通的组，从而避免在一个时间段内集中回写电流。

公开(公告)号：US07940577B2

公开(公告)日：2011-05-10

申请号：US11592978

申请日：2006-11-06

申请人： Kenjyu Shimogawa ,  Hiroshi Furuta

发明人： Kenjyu Shimogawa ,  Hiroshi Furuta

IPC分类号： G11C7/00

CPC分类号： G11C5/14

摘要： The semiconductor integrated circuit device includes a voltage control circuit that generates a control voltage for deactivating a field effect transistor by a gate voltage. The voltage control circuit controls a voltage so as to substantially minimize the leakage current which flows when the field effect transistor is inactive with respect to a device temperature.

摘要翻译： 半导体集成电路器件包括电压控制电路，其产生用于通过栅极电压去激活场效应晶体管的控制电压。 电压控制电路控制电压，以使得当场效应晶体管相对于器件温度无效时流过的漏电流基本上最小化。

公开(公告)号：US20100326959A1

公开(公告)日：2010-12-30

申请号：US12880819

申请日：2010-09-13

申请人： Yukio Kanazawa ,  Masahiro Hanai ,  Hiroshi Furuta

发明人： Yukio Kanazawa ,  Masahiro Hanai ,  Hiroshi Furuta

IPC分类号： H01H33/91

CPC分类号： H01H1/0015 ,  H01H33/7076 ,  H01H33/901 ,  H01H2001/0026

摘要： The invention provides a gas insulated switchgear, and a method for detecting arc damage in a part used in a gas insulated switchgear, which detect directly when an electric contact or a peripheral part reaches an initially set wear limit. An insulating nozzle of a circuit breaker contains a marking substance that releases a gaseous substance inside a circuit breaker gas container as a result of wear by an arc. For ensuring heat resistance and insulation properties, the insulating nozzle is ordinarily formed of a fluororesin, but in the present invention, it is formed of the ordinarily used fluororesin having uniformly mixed therein, as the marking substance, a chlorine-containing resin which has excellent heat resistance and insulation properties such as polyvinylidene chloride.

摘要翻译： 本发明提供了一种气体绝缘开关装置，以及用于检测在气体绝缘开关装置中使用的部件中的电弧损伤的方法，其在电接触或周边部分达到初始设定的磨损极限时直接检测。 断路器的绝缘喷嘴包含由于电弧磨损而将断路器气体容器内的气态物质释放的标记物质。 为了确保耐热性和绝缘性，绝缘喷嘴通常由氟树脂形成，但是在本发明中，由通常使用的均匀混合的氟树脂作为标记物质，具有优异的含氯树脂 耐热性和绝缘性能如聚偏二氯乙烯。

公开(公告)号：US20100320539A1

公开(公告)日：2010-12-23

申请号：US12801216

申请日：2010-05-27

申请人： Hiroshi Furuta

发明人： Hiroshi Furuta

IPC分类号： H01L27/12 ,  H01L27/088

CPC分类号： H01L27/1203 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has an SOI (Silicon On Insulator) structure and comprising a P-channel FET and an N-channel FET which are formed on an insulating film. The semiconductor device includes: at least two of first, second, third and fourth PN-junction elements. The first PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of source/drain regions of the P-channel FET and the N-channel FET, respectively. The second PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the source/drain region and a channel region in the P-channel FET, respectively. The third PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of a channel region and the source/drain region in the N-channel FET, respectively. The fourth PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the channel regions of the N-channel FET and the P-channel FET, respectively. At least two PN-junction elements are connected in series in a forward bias between two different terminals to form an electrostatic protection device.

摘要翻译： 半导体器件具有SOI（绝缘体上硅）结构，并且包括形成在绝缘膜上的P沟道FET和N沟道FET。 半导体器件包括：第一，第二，第三和第四PN结元件中的至少两个。 第一PN结元件分别由P型半导体层和具有与P沟道FET和N沟道FET的源/漏区相同的杂质浓度的N型半导体层形成。 第二PN结元件分别由P型半导体层和与P沟道FET中的源/漏区和沟道区相同的杂质浓度的N型半导体层形成。 第三PN结元件由P型半导体层和与N沟道FET中的沟道区和源极/漏极区相同的杂质浓度的N型半导体层分别形成。 第四PN结元件分别由具有与N沟道FET和P沟道FET的沟道区相同的杂质浓度的P型半导体层和N型半导体层形成。 至少两个PN结元件在两个不同端子之间的正向偏压中串联连接以形成静电保护装置。

公开(公告)号：US07719879B2

公开(公告)日：2010-05-18

申请号：US11386811

申请日：2006-03-23

申请人： Muneaki Matsushige ,  Hiroyuki Satake ,  Hiroshi Furuta ,  Toshifumi Takahashi ,  Hideyuki Nakamura

发明人： Muneaki Matsushige ,  Hiroyuki Satake ,  Hiroshi Furuta ,  Toshifumi Takahashi ,  Hideyuki Nakamura

IPC分类号： G11C11/00

CPC分类号： H01L27/1104 ,  G11C11/412

摘要： A semiconductor integrated circuit includes a word line extending along a first direction, a first and a second N-well regions, a P-well region disposed between the first and the second N-well regions, a memory cell having a first, second, third, and fourth PMOS transistors, and a first and second NMOS transistors, the first and the second PMOS transistors disposed in the first N-well region along a second direction which is different from the first direction, the first and the second NMOS transistors disposed in the P-well region, and the third and the fourth PMOS transistors disposed in the second N-well region along the second direction.

摘要翻译： 半导体集成电路包括沿着第一方向延伸的字线，第一和第二N阱区域，设置在第一和第二N阱区域之间的P阱区域，具有第一，第二， 第三和第四PMOS晶体管，以及第一和第二NMOS晶体管，第一和第二PMOS晶体管沿着与第一方向不同的第二方向设置在第一N阱区域中，第一和第二NMOS晶体管被布置 以及沿第二方向设置在第二N阱区中的第三和第四PMOS晶体管。

公开(公告)号：US20080135978A1

公开(公告)日：2008-06-12

申请号：US11987854

申请日：2007-12-05

申请人： Hiroshi Furuta

发明人： Hiroshi Furuta

IPC分类号： H01L27/00

CPC分类号： H01L27/0248 ,  H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor.

摘要翻译： 半导体集成电路器件包括连接到电源端子的电源线，连接到接地端子的接地线和并联在电源线和接地线之间的多个电容器。 多个电容器包括布置在离终端之一的第一距离处的第一电容器和布置成距离一个端子的第一距离大的第二距离的第二电容器，并且第一电容器具有比 第二电容器。

公开(公告)号：US20070063288A1

公开(公告)日：2007-03-22

申请号：US11504074

申请日：2006-08-15

申请人： Hiroshi Furuta ,  Hiroyuki Takahashi

发明人： Hiroshi Furuta ,  Hiroyuki Takahashi

IPC分类号： H01L29/94

CPC分类号： H01L27/092 ,  H01L27/0207 ,  H01L27/1104

摘要： A semiconductor device according to an embodiment of the invention includes: a plurality of field effect transistors; and a plurality of logic circuits composed of the field effect transistors, the field effect transistors each including: first and second drain regions formed away from each other; at least one source region formed between the first and second drain regions; and a plurality of gate electrodes formed between the first drain region and the source region and between the second drain region and the source region.

摘要翻译： 根据本发明实施例的半导体器件包括：多个场效应晶体管; 以及由场效应晶体管构成的多个逻辑电路，所述场效应晶体管分别包括：彼此远离形成的第一和第二漏极区域; 形成在所述第一和第二漏极区之间的至少一个源极区; 以及形成在所述第一漏极区域和所述源极区域之间以及所述第二漏极区域和所述源极区域之间的多个栅极电极。

公开(公告)号：US20070048921A1

公开(公告)日：2007-03-01

申请号：US11503203

申请日：2006-08-14

申请人： Takami Nagata ,  Hiroshi Furuta

发明人： Takami Nagata ,  Hiroshi Furuta

IPC分类号： H01L21/8238

CPC分类号： H01L21/823456 ,  H01L21/32139 ,  H01L27/11 ,  H01L27/1104

摘要： A method of manufacturing a semiconductor device includes performing a first etching process on a gate electrode layer to form a gate electrode of a first transistor group including a transistor pair, and performing a second etching process different from the first etching on the gate electrode layer to form a gate electrode of a second transistor group. Forming in this way enables characteristics of the transistor pair to be the same.

摘要翻译： 一种制造半导体器件的方法包括：在栅电极层上进行第一蚀刻工艺以形成包括晶体管对的第一晶体管组的栅电极，并且执行与栅极电极层上的第一蚀刻不同的第二蚀刻工艺， 形成第二晶体管组的栅电极。 以这种方式形成使晶体管对的特性相同。