公开(公告)号：US07719879B2

公开(公告)日：2010-05-18

申请号：US11386811

申请日：2006-03-23

申请人： Muneaki Matsushige ,  Hiroyuki Satake ,  Hiroshi Furuta ,  Toshifumi Takahashi ,  Hideyuki Nakamura

发明人： Muneaki Matsushige ,  Hiroyuki Satake ,  Hiroshi Furuta ,  Toshifumi Takahashi ,  Hideyuki Nakamura

IPC分类号： G11C11/00

CPC分类号： H01L27/1104 ,  G11C11/412

摘要： A semiconductor integrated circuit includes a word line extending along a first direction, a first and a second N-well regions, a P-well region disposed between the first and the second N-well regions, a memory cell having a first, second, third, and fourth PMOS transistors, and a first and second NMOS transistors, the first and the second PMOS transistors disposed in the first N-well region along a second direction which is different from the first direction, the first and the second NMOS transistors disposed in the P-well region, and the third and the fourth PMOS transistors disposed in the second N-well region along the second direction.

摘要翻译： 半导体集成电路包括沿着第一方向延伸的字线，第一和第二N阱区域，设置在第一和第二N阱区域之间的P阱区域，具有第一，第二， 第三和第四PMOS晶体管，以及第一和第二NMOS晶体管，第一和第二PMOS晶体管沿着与第一方向不同的第二方向设置在第一N阱区域中，第一和第二NMOS晶体管被布置 以及沿第二方向设置在第二N阱区中的第三和第四PMOS晶体管。

公开(公告)号：US06258708B1

公开(公告)日：2001-07-10

申请号：US09039768

申请日：1998-03-16

申请人： Toshifumi Takahashi

发明人： Toshifumi Takahashi

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1112

摘要： There is provided a method of fabricating a semiconductor device, including the steps of forming a silicon oxide film on a semiconductor substrate for defining device isolation regions therewith, forming a gate oxide film over the product resulting from the previous step, forming an electrically conductive film over the product resulting from the previous step, forming a first insulating film over the electrically conductive film, etching the first insulating film and the electrically conductive film to thereby form a first wiring layer comprising a plurality of sections, forming a second insulating film around a sidewall of the sections of the first wiring layer, forming a first interlayer insulating film over the product resulting from the previous step, simultaneously forming a first contact hole reaching the semiconductor substrate and a second contact hole reaching the first wiring layer, forming a second wiring layer over the product resulting from the previous step, forming a second interlayer insulating film over the product resulting from the previous step, simultaneously forming a third contact hole reaching the semiconductor substrate and a fourth contact hole reaching the second wiring layer, forming a contact plug in each of the third and fourth contact holes, and forming a third wiring layer on the second interlayer insulating film so as to make contact with the contact plug. The above-mentioned method reduces the number of masks to be used for fabricating a semiconductor device, ensuring the enhancement of productivity, and presents the greater designability of forming a contact hole above a gate.

摘要翻译： 提供了一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成氧化硅膜，用于限定器件隔离区，从上一步骤产生的产品上形成栅极氧化膜，形成导电膜 在上述步骤产生的产品上，在导电膜上形成第一绝缘膜，蚀刻第一绝缘膜和导电膜，从而形成包括多个部分的第一布线层，在第一绝缘膜周围形成第二绝缘膜 在所述第一布线层的所述部分的侧壁上形成由所述前一步骤产生的产品上的第一层间绝缘膜，同时形成到达所述半导体衬底的第一接触孔和到达所述第一布线层的第二接触孔，形成第二布线 在上一步产生的产品上形成一层 在上述步骤产生的产品上，同时形成到达半导体衬底的第三接触孔和到达第二布线层的第四接触孔，在第三和第四接触孔中的每一个中形成接触插塞，并形成 在第二层间绝缘膜上的第三布线层，以便与接触插塞接触。 上述方法减少了用于制造半导体器件的掩模的数量，确保提高生产率，并且在栅极上方形成接触孔的更大的可设计性。

公开(公告)号：US6118170A

公开(公告)日：2000-09-12

申请号：US228752

申请日：1999-01-12

申请人： Toshifumi Takahashi ,  Keita Kumamoto

发明人： Toshifumi Takahashi ,  Keita Kumamoto

IPC分类号： H01C13/00 ,  H01C7/00 ,  H01C17/06 ,  H01L21/265 ,  H01L21/822 ,  H01L23/528 ,  H01L27/04 ,  H01L27/11 ,  H01L29/00

CPC分类号： H01L21/76895 ,  H01L23/528 ,  H01L27/1112 ,  H01L2924/0002

摘要： In a resistance element formed by a connection layer including a flexing portion, the connection layer is constructed by a high resistance section including the flexing portion and a low resistance section. Boundaries between the high resistance section and the low resistance section are approximately in parallel with a bisector of the connection layer at the flexing portion.

摘要翻译： 在由包括弯曲部分的连接层形成的电阻元件中，连接层由包括弯曲部分和低电阻部分的高电阻部分构成。 高电阻部分和低电阻部分之间的边界与弯曲部分处的连接层的平分线大致平行。

公开(公告)号：US5909047A

公开(公告)日：1999-06-01

申请号：US866269

申请日：1997-05-30

申请人： Toshifumi Takahashi

发明人： Toshifumi Takahashi

IPC分类号： H01L21/8244 ,  H01L27/02 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/1104 ,  H01L27/0207 ,  Y10S257/903

摘要： A semiconductor memory device capable of high-speed operation, low-voltage operation, and low power-consumption. First and second driver transistors are laid out in such a way that the channel regions of first and second driver transistors extend in a direction oblique to first and second word lines. First and second transfer transistors are laid out in such a way that the channel regions of the first and second transfer transistors extend in a direction perpendicular to the first and second word lines. The channel regions of the first and second transfer transistors and the contact resistance of the first and second bit contacts are substantially constant independent of an allowable overlay error, respectively, thereby keeping the capability of the first and second transfer transistors and the bit contact resistance the same independent of the allowable overlay error.

摘要翻译： 一种半导体存储器件，其能够进行高速运行，低电压运行和低功耗。 第一和第二驱动器晶体管被布置成使得第一和第二驱动晶体管的沟道区域沿与第一和第二字线相反的方向延伸。 第一和第二传输晶体管布置成使得第一和第二传输晶体管的沟道区域在垂直于第一和第二字线的方向上延伸。 第一和第二传输晶体管的沟道区域和第一和第二位触点的接触电阻分别基本上是恒定的，与允许的重叠误差无关，从而保持第一和第二传输晶体管的能力以及位接触电阻 相同的独立于允许的重叠错误。

公开(公告)号：US4667586A

公开(公告)日：1987-05-26

申请号：US802333

申请日：1985-11-26

申请人： Tsutomu Harada ,  Toshifumi Takahashi

发明人： Tsutomu Harada ,  Toshifumi Takahashi

IPC分类号： A47J31/36 ,  A47J31/40 ,  G07F13/00 ,  G07F13/06 ,  A47J31/00

CPC分类号： G07F13/065 ,  A47J31/3614

摘要： Beverage brewing apparatus suitable for use in a vending machine has a frame supporting a vertically movable open bottom cylinder and a piston slidably disposed within the cylinder. A brewing cavity is disposed beneath the cylinder to enable reciprocation horizontally between a brewing position and a rest position. The horizontal movement of the cavity is controlled through a cable running around a pulley rotatably supported on the frame. The pulley is provided with a mechanism for adjusting the position thereof to determine the brewing position and rest position of the cavity to ensure secure engagement between the cylinder and brewing cavity.

摘要翻译： 适用于自动售货机的饮料冲泡设备具有支撑可垂直移动的开放底部圆筒和可滑动地设置在圆筒内的活塞的框架。 冲泡腔设置在气缸下方以使得能够在冲泡位置和静止位置之间水平往复运动。 空腔的水平运动通过围绕可旋转地支撑在框架上的皮带轮运行的电缆来控制。 滑轮设置有用于调节其位置以确定空腔的冲泡位置和静止位置的机构，以确保气缸和冲泡腔之间的牢固接合。

公开(公告)号：US20110316052A1

公开(公告)日：2011-12-29

申请号：US13150842

申请日：2011-06-01

申请人： Hiroshi FURUTA ,  Takaaki KOBAYASHI ,  Hirofumi AZUHATA ,  Tomoya MORITA ,  Ryuichi OKAMURA ,  Toshifumi TAKAHASHI

发明人： Hiroshi FURUTA ,  Takaaki KOBAYASHI ,  Hirofumi AZUHATA ,  Tomoya MORITA ,  Ryuichi OKAMURA ,  Toshifumi TAKAHASHI

IPC分类号： H01L27/088

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region 40 arranged between the functional circuit regions and between the memory macro region 10 and the functional circuit regions and including a dummy pattern. The dummy pattern has a pattern identical to that of diffusion layers and gate electrodes of a memory cell pattern in a memory cell array region. An area ratio of dummy diffusion layer(s) and dummy gate electrode(s) in the dummy pattern region is equal to or greater than that of the diffusion layers and the gate electrode(s) in the memory cell array region.

摘要翻译： 除了存储器宏区域和基板上的功能电路区域之外，半导体集成电路器件还包括布置在功能电路区域之间以及存储器宏区域10和功能电路区域之间并包括虚拟图案的虚设图案区域40。 虚设图案具有与存储单元阵列区域中的存储单元图案的扩散层和栅电极相同的图案。 虚设图形区域中的虚设扩散层和伪栅电极的面积比等于或大于存储单元阵列区域中的扩散层和栅电极的面积比。

公开(公告)号：US08030142B2

公开(公告)日：2011-10-04

申请号：US11798735

申请日：2007-05-16

申请人： Toshifumi Takahashi

发明人： Toshifumi Takahashi

IPC分类号： H01L21/82 ,  H01L21/00 ,  H01L21/84

CPC分类号： G06F17/5072 ,  G06F17/5081

摘要： A semiconductor device according to an embodiment of the present invention includes: a first region having patterns formed based on grid points as intersections of grid lines; and a second region including a plurality of layout cells an outer edge of which is defined by the grid points, the layout cells having patterns formed based on a wiring rule with patterns connected to patterns of the first region among the patterns being formed based on the grid points at a boundary with the first region.

摘要翻译： 根据本发明的实施例的半导体器件包括：第一区域，其具有基于网格点形成的图案，作为网格线的交点; 以及第二区域，其包括多个布局单元，其外边缘由网格点限定，所述布局单元具有基于布线规则形成的图案，所述布线规则具有连接到所述图案中的所述第一区域的图案的图案， 网格点与第一个区域的边界。

公开(公告)号：US07763516B2

公开(公告)日：2010-07-27

申请号：US12285391

申请日：2008-10-03

申请人： Toshifumi Takahashi

发明人： Toshifumi Takahashi

IPC分类号： H01L21/8234

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11

摘要： A manufacturing method of semiconductor device includes: forming a nitride film above a silicon substrate including a first region and a second region which respectively correspond to an outside of a memory cell region and the memory cell region; forming trenches reaching from the nitride film to the silicon substrate; retreating the nitride film such that widths of the trenches at the nitride film become wider; forming a buried oxide film to be buried in the trenches after the retreating; polishing the buried oxide film with the nitride film being used as a stopper; removing the nitride film after the polishing; implanting impurity after the removing; forming gate electrodes after the implanting; and implanting impurity after the forming the gate electrodes.

摘要翻译： 半导体器件的制造方法包括：在包括分别对应于存储单元区域和存储单元区域的外部的第一区域和第二区域的硅衬底上形成氮化物膜; 形成从氮化膜到硅衬底到达的沟槽; 使氮化膜退回，使得氮化膜的沟槽宽度变宽; 在后退后形成埋入氧化膜以埋藏在沟槽中; 用氮化物膜作为止动器抛光埋置的氧化膜; 抛光后除去氮化膜; 去除后注入杂质; 在植入后形成栅电极; 以及在形成栅电极之后注入杂质。

公开(公告)号：US06566216B1

公开(公告)日：2003-05-20

申请号：US09465745

申请日：1999-12-17

申请人： Toshifumi Takahashi

发明人： Toshifumi Takahashi

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： To provide a semiconductor device and a process for manufacturing the same which is capable of suppressing short channel effect and preventing a current from leaking between a contact and a silicon substrate. The semiconductor device of the present invention comprises a silicon substrate on which a source/drain area (3 in FIG. 1), a silicon oxide layer (4 in FIG. 1) and a silicon nitride layer (5 in FIG. 1) are successively formed in this order, and a trench which extend through said layers to split the source/drain area. A columnar gate electrode (9 in FIG. 1) is formed within the trench in such a manner that it is spaced from the inner wall of the trench and a lightly doped drain (LDD) area (10 in FIG. 1) is formed at an area of the bottom of the trench in which no gate electrode is disposed. In such a structure, the short channel effect which occurs in association with reduction in the gate length is suppressed.

摘要翻译： 提供能够抑制短路效应并防止电流在接触体和硅基板之间泄漏的半导体装置及其制造方法。 本发明的半导体器件包括其上源极/漏极区域（图1中的3），氧化硅层（图1中的4）和氮化硅层（图1中的5）在其上的硅衬底 依次形成，并且延伸穿过所述层以分裂源/漏区的沟槽。 在沟槽内形成柱状栅电极（图1中的9），使得其与沟槽的内壁间隔开，并且形成轻掺杂漏极（LDD）区域（图1中的10） 沟槽底部的没有设置栅电极的区域。 在这种结构中，与栅极长度的减小相关联地发生的短沟道效应被抑制。

公开(公告)号：US06246080B1

公开(公告)日：2001-06-12

申请号：US09307748

申请日：1999-05-10

申请人： Toshifumi Takahashi ,  Keita Kumamoto

发明人： Toshifumi Takahashi ,  Keita Kumamoto

IPC分类号： H01L2976

CPC分类号： H01L29/4238

摘要： A semiconductor device comprising, on a semiconductor substrate, an element-isolating region, an active region, and a gate electrode with a bent portion having a bent-angle &thgr; on the active region. The boundary between the element-isolating region and the active region intersects the gate electrode so that the line segments of the boundary at which said intersection takes place, are approximately parallel to the bisector of the bent-angle &thgr; of the bent portion of the gate electrode. In this semiconductor device, the variation in width of gate electrode is small and accordingly the variation in properties is small, even when the relative position of gate electrode and active region of MOSFET has shifted slightly.

摘要翻译： 一种半导体器件，包括在半导体衬底上的元件隔离区域，有源区域和具有在有源区域上具有弯曲角θ的弯曲部分的栅电极。 元件隔离区域和有源区域之间的边界与栅电极相交，使得发生所述交点的边界的线段大致平行于栅极的弯曲部分的弯曲角度的二等分线 电极。 在该半导体器件中，即使MOSFET的有源区域的栅极相对位置略微偏移，栅电极的宽度变化也小，因此其特性变动小。