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145 条记录 (耗时 0.034 秒)

    Integrated circuit device and electronic instrument
    23.
    发明申请
    Integrated circuit device and electronic instrument 有权
    集成电路器件和电子仪器

    公开(公告)号：US20070001973A1

    公开(公告)日：2007-01-04

    申请号：US11270632

    申请日：2005-11-10

    申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Katsuhiko Maki

    发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Katsuhiko Maki

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3611 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2360/18

    摘要： An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a logic circuit block LB, a grayscale voltage generation circuit block GB, data driver blocks DB1 to DB4, and a power supply circuit block PB. The data driver blocks DB1 to DB4 are disposed between the logic circuit block LB and the grayscale voltage generation circuit block GB, and the power supply circuit block PB.

    摘要翻译： 一种集成电路装置，包括沿着第一方向D 1布置的第一至第N电路块CB 1至CBN，当第一方向D 1是从集成电路器件的第一侧朝向与第一方向相反的第三侧的方向时 所述第一侧为短边，当第二方向D 2为从所述集成电路器件的第二侧朝向与所述第二侧相反的第四侧的方向时，所述第二侧为长边。 电路块CB 1至CBN包括逻辑电路块LB，灰度电压产生电路块GB，数据驱动器块DB 1至DB 4和电源电路块PB。 数据驱动器块DB 1至DB 4设置在逻辑电路块LB和灰度级电压产生电路块GB之间，以及电源电路块PB。

    Integrated circuit device and electronic instrument
    24.
    发明申请
    Integrated circuit device and electronic instrument 有权
    集成电路器件和电子仪器

    公开(公告)号：US20070001969A1

    公开(公告)日：2007-01-04

    申请号：US11270552

    申请日：2005-11-10

    申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

    发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3688 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2310/027

    摘要： An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines. The display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines WL, a plurality of bitlines BL, a plurality of memory cells MC, and a data read control circuit. Each of the RAM blocks is disposed along a first direction X in which the bitlines BL extend. The data read control circuit controls data reading so that data for pixels corresponding to the signal lines is read out by N times reading in one horizontal scan period 1H of the display panel (N is an integer larger than 1)

    摘要翻译： 集成电路装置具有显示存储器，其存储显示在具有多条扫描线和多条数据线的显示面板中的至少一帧的数据。 显示存储器包括多个RAM块，每个RAM块包括多个字线WL，多个位线BL，多个存储单元MC和数据读取控制电路。 每个RAM块沿着位线BL延伸的第一方向X设置。 数据读取控制电路控制数据读取，使得对应于信号线的像素的数据在显示面板的一个水平扫描周期1H（N是大于1的整数）中读出N次读数，

    Reproduction apparatus and reproduction method
    25.
    发明申请
    Reproduction apparatus and reproduction method 失效
    繁殖装置和再现方法

    公开(公告)号：US20060010099A1

    公开(公告)日：2006-01-12

    申请号：US11171493

    申请日：2005-06-30

    申请人： Naoko Takeda ,  Kissei Matsumoto ,  Takashi Kumagai ,  Toshihide Ooba ,  Hiroshi Iwata ,  Shingo Yamade

    发明人： Naoko Takeda ,  Kissei Matsumoto ,  Takashi Kumagai ,  Toshihide Ooba ,  Hiroshi Iwata ,  Shingo Yamade

    IPC分类号： G06F17/30

    CPC分类号： G06F3/0482 ,  G06F3/04892

    摘要： To provide a reproduction apparatus able to easily select a desired content data based on an attribute of the content data by a simple operation from a user and a reproduction method for the same, wherein the reproduction apparatus having: a display displaying the item; a first operation unit instructing a switch of the attribute; a second function unit instructing a selection of a predetermined item on the display; and a processing unit switching a first screen from a screen of a plurality of items so as to display a plurality of items when the first operation key is operated, and switching to a second screen displaying a plurality of item when the second operation key is operated when a plurality of item is displayed on the first screen.

    摘要翻译： 为了提供能够通过用户的简单操作基于内容数据的属性容易地选择期望的内容数据的再现设备及其再现方法，其中所述再现设备具有：显示该项目的显示; 第一操作单元，指示所述属性的切换; 指示在显示器上选择预定项目的第二功能单元; 以及处理单元，从多个项目的屏幕切换第一屏幕，以便当第一操作键被操作时显示多个项目，并且当第二操作键被操作时切换到显示多个项目的第二屏幕 当在第一屏幕上显示多个项目时。

    Semiconductor memory device and method of fabricating the same
    26.
    发明授权
    Semiconductor memory device and method of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US06534864B1

    公开(公告)日：2003-03-18

    申请号：US09428821

    申请日：1999-10-28

    申请人： Kazuo Tanaka ,  Takashi Kumagai ,  Junichi Karasawa ,  Kunio Watanabe

    发明人： Kazuo Tanaka ,  Takashi Kumagai ,  Junichi Karasawa ,  Kunio Watanabe

    IPC分类号： H01L2348

    CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

    摘要： A semiconductor memory device (SRAM) comprises memory cells, each of which includes two load transistors, two driver transistors and two transfer transistors. The SRAM cell includes a semiconductor substrate in which the transistors are formed, a first interlayer dielectric formed on the semiconductor substrate, first contact portions formed in the first interlayer dielectric and first wiring layers (node wiring layers and pad layers) formed on the first interlayer dielectric. The first contact portions and the first wiring layers include metal layers made of refractory metal and a refractory metal nitride layers. This semiconductor memory device of the present invention is capable of enhancing an integration degree of wiring layers and achieving a microfabrication.

    摘要翻译： 半导体存储器件（SRAM）包括存储单元，每个存储单元包括两个负载晶体管，两个驱动晶体管和两个转移晶体管。 SRAM单元包括其中形成晶体管的半导体衬底，形成在半导体衬底上的第一层间电介质，形成在第一层间电介质中的第一接触部分和形成在第一层间电介质上的第一布线层（节点布线层和衬垫层） 电介质。 第一接触部分和第一布线层包括由难熔金属制成的金属层和难熔金属氮化物层。 本发明的半导体存储器件能够提高布线层的集成度并实现微细加工。

    Semiconductor memory device and method of fabricating the same
    27.
    发明授权
    Semiconductor memory device and method of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US06232670B1

    公开(公告)日：2001-05-15

    申请号：US09361043

    申请日：1999-07-26

    申请人： Takashi Kumagai ,  Junichi Karasawa ,  Kazuo Tanaka ,  Kunio Watanabe

    发明人： Takashi Kumagai ,  Junichi Karasawa ,  Kazuo Tanaka ,  Kunio Watanabe

    IPC分类号： H01L2711

    CPC分类号： H01L27/1104

    摘要： First and second memory cells of an SRAM comprises first, second, and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer diverges from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The pattern of the first, second, and third conductive layers of the second memory cell is a rotated pattern of the first, second, and third conductive layers in the first memory cell at an angle of 180 degrees around an axis perpendicular to the main surface of a semiconductor substrate.

    摘要翻译： SRAM的第一和第二存储单元包括第一，第二和第三导电层。 第一导电层是用于第一负载晶体管和第一驱动晶体管的栅电极。 第二导电层从场氧化物区域上的第一导电层发散，并且电连接到第二驱动器晶体管有源区。 第三导电层是用于第二负载晶体管的栅电极和第二驱动晶体管。 第三导电层电连接到第一负载晶体管有源区。 第二存储单元的第一，第二和第三导电层的图案是第一存储单元中的第一，第二和第三导电层的旋转图案，围绕垂直于主表面的轴以180度的角度 的半导体衬底。

    Display panel apparatus having reduced capacitive coupling
    28.
    发明授权
    Display panel apparatus having reduced capacitive coupling 失效
    具有减小的电容耦合的显示面板装置

    公开(公告)号：US06181071B2

    公开(公告)日：2001-01-30

    申请号：US09031609

    申请日：1998-02-27

    申请人： Akimasa Yuuki ,  Mitsumasa Umesaki ,  Sadayuki Matsumoto ,  Takashi Kumagai ,  Shin Kawabe

    发明人： Akimasa Yuuki ,  Mitsumasa Umesaki ,  Sadayuki Matsumoto ,  Takashi Kumagai ,  Shin Kawabe

    IPC分类号： G02F1335

    CPC分类号： G02F1/133615

    摘要： A display panel with a reduced capacitive coupling. The panel includes a transmission type liquid crystal panel. A lamp is provided adjacent at least one side of a light guide plate to guide the light to the crystal panel. A high frequency current supply is used to power the light. A reflective plate encircles the lamp so as to introduce the light to the light guide plate. A housing is made of a thin metal plate. Each portion of the housing is connected with a common electrical potential. Part of the housing extends away from the reflective plate around the lamp or contains an opening in the same location. By this arrangement, the capacitance between the reflective plate and the housing is made smaller thus reducing the leakage current.

    摘要翻译： 具有降低电容耦合的显示面板。 面板包括透射型液晶面板。 在导光板的至少一侧附近设置灯以将光引导到晶体面板。 使用高频电流源供电。 反射板围绕灯，以将光引入导光板。 外壳由薄金属板制成。 壳体的每个部分与公共电位相连。 壳体的一部分远离灯的反射板延伸，或者在相同位置处包含开口。 通过这种布置，使反射板和壳体之间的电容变小，从而减小漏电流。

    Semiconductor storage device and electronic equipment using the same
    29.
    发明授权
    Semiconductor storage device and electronic equipment using the same 失效
    半导体存储装置及使用其的电子设备

    公开(公告)号：US6044028A

    公开(公告)日：2000-03-28

    申请号：US891822

    申请日：1997-07-14

    申请人： Yasuhiko Tomohiro ,  Takashi Kumagai

    发明人： Yasuhiko Tomohiro ,  Takashi Kumagai

    IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C8/14 ,  G11C11/40 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C11/418 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C11/418 ,  G11C29/02 ,  G11C8/14

    摘要： A semiconductor storage device which can prevent a short-circuit current from flowing therethrough even if a short circuit occurs between main word lines and bit lines. The semiconductor storage device has a plurality of normal memory cell array blocks, each including multiple columns of bit line pairs, sub word lines and normal memory cells. The semiconductor storage device also includes main word lines extending through the plurality of normal memory cell array blocks, a main row selecting decoder for selecting one of the main word lines on the basis of a main row address signal, a sub row selecting decoder for selecting one of the sub word lines depending on one of the main word lines on the basis of a sub row address signal, and a pre-charge circuit for pre-charging a pair of bit lines. The main row selecting decoder has a first setting circuit for inactivating the main word line at a high level potential substantially equal to a potential of a pre-charged bit line pair, while at a low level potential, the main word line is activated. The sub row selecting decoder has a second setting circuit for inactivating the sub word lines when the main word line is in the high level potential. The second setting circuit has an inverting element for receiving and inverting a signal from the main word line, the inverted signal being then outputted therefrom, and a switch for inactivating the sub word lines when the output of the inverting element is in the low level potential.

    摘要翻译： 即使在主字线和位线之间发生短路，也能够防止短路电流流过的半导体存储装置。 半导体存储装置具有多个正常存储单元阵列块，每个存储单元阵列块包括多列位线对，子字线和正常存储单元。 半导体存储装置还包括延伸穿过多个正常存储单元阵列块的主字线，用于基于主行地址信号选择主字线之一的主行选择解码器，用于选择的主行选择解码器 取决于基于子行地址信号的主字线之一的子字线之一和用于对一对位线进行预充电的预充电电路。 主行选择解码器具有第一设置电路，用于在基本上等于预充电位线对的电位的高电平电位下使主字线失活，而在低电平电位下，主字线被激活。 子行选择解码器具有第二设置电路，用于当主字线处于高电平电位时使子字线失活。 第二设定电路具有反相器件，用于接收和反相来自主字线的信号，然后从其输出反相信号，以及用于在反相元件的输出处于低电平电位时使子字线失活的开关 。

    Light source lighting device including a constant-current supply that is connected to a light source and supplies a constant current of a substantially constant magnitude to the light source, and luminaire
    30.
    发明授权
    Light source lighting device including a constant-current supply that is connected to a light source and supplies a constant current of a substantially constant magnitude to the light source, and luminaire 有权
    光源照明装置，其包括连接到光源并且向光源提供基本恒定幅度的恒定电流的恒流源，以及照明器

    公开(公告)号：US08710750B2

    公开(公告)日：2014-04-29

    申请号：US13274617

    申请日：2011-10-17

    申请人： Takafumi Nonaka ,  Takashi Kumagai ,  Yuichiro Ito ,  Haruka Kinoshita ,  Shinsuke Funayama ,  Takashi Maeda

    发明人： Takafumi Nonaka ,  Takashi Kumagai ,  Yuichiro Ito ,  Haruka Kinoshita ,  Shinsuke Funayama ,  Takashi Maeda

    IPC分类号： H05B39/00

    CPC分类号： H05B33/0815 ,  Y02B20/347

    摘要： A power supply circuit drives circuits having different numbers of series-connected LEDs without changing a circuit constant or a component. An LED series circuit is connected to a power converter circuit of a power supply circuit. The power converter circuit is controlled by a control arithmetic circuit, and supplies a constant current to the LED series circuit. A voltage detection circuit detects a voltage applied to the LED series circuit. The control arithmetic circuit checks whether the LED series circuit has 40 LEDs or 20 LEDs, based on the voltage detected by the voltage detection circuit. The control arithmetic circuit holds a constant-current value table for 40 LEDs and a constant-current value table for 20 LEDs. In accordance with the detected voltage, the control arithmetic circuit selects one constant-current value table, and controls the power converter circuit based on the constant-current value table selected.

    摘要翻译： 电源电路驱动具有不同数量的串联LED的电路，而不改变电路常数或部件。 LED串联电路连接到电源电路的电源转换器电路。 功率转换器电路由控制运算电路控制，并向LED串联电路提供恒定电流。 电压检测电路检测施加到LED串联电路的电压。 控制运算电路根据电压检测电路检测出的电压，检查LED串联电路是否具有40个LED或20个LED。 控制运算电路保存40个LED的恒定电流值表和20个LED的恒定电流值表。 根据检测到的电压，控制运算电路选择一个恒流值表，并根据所选择的恒流值表控制功率转换电路。