公开(公告)号：US07701778B2

公开(公告)日：2010-04-20

申请号：US11684035

申请日：2007-03-09

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C11/34

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US20090244972A1

公开(公告)日：2009-10-01

申请号：US12400015

申请日：2009-03-09

申请人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

发明人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

IPC分类号： G11C14/00 ,  G11C16/04 ,  G11C7/06

CPC分类号： G11C16/045 ,  G11C16/0441 ,  G11C16/12 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558

摘要： A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

摘要翻译： 非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

公开(公告)号：US07573742B2

公开(公告)日：2009-08-11

申请号：US11550335

申请日：2006-10-17

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

IPC分类号： G11C16/04

CPC分类号： G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568

摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行位数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

公开(公告)号：US20080273387A1

公开(公告)日：2008-11-06

申请号：US10598853

申请日：2005-11-01

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568

摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行位数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

公开(公告)号：US06421034B1

公开(公告)日：2002-07-16

申请号：US09373114

申请日：1999-08-12

申请人： Masaaki Mihara

发明人： Masaaki Mihara

IPC分类号： G09G330

CPC分类号： G09G3/30 ,  G09G2320/043 ,  G09G2320/0626 ,  G09G2330/024

摘要： A serial resonant circuit, formed by EL panel (CEL) and coil (L1), is connected to a push-pull driver through a positive feedback path to form an oscillator circuit. The EL panel is driven by a sinusoidal driving signal to emit light. The voltage level of the EL panel driving signal is adjusted corresponding to the change in the capacitance of the EL panel so that the luminous brightness of the EL panel can be maintained on a constant level.

摘要翻译： 由EL面板（CEL）和线圈（L1）形成的串联谐振电路通过正反馈路径连接到推挽驱动器，以形成振荡电路。 EL面板由正弦驱动信号驱动，发光。 根据EL面板的电容变化来调整EL面板驱动信号的电压电平，使得EL面板的发光亮度能够保持恒定。

公开(公告)号：US06387745B1

公开(公告)日：2002-05-14

申请号：US09457715

申请日：1999-12-10

申请人： Hiroshi Onoda ,  Masaaki Mihara ,  Hiroshi Takada

发明人： Hiroshi Onoda ,  Masaaki Mihara ,  Hiroshi Takada

IPC分类号： H01L218234

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546

摘要： An aluminum wire is connected to a P-type layer of a polydiode element through a resistive element consisting of a barrier metal film and a tungsten plug. Another aluminum wire is connected to an N-type layer of the polydiode element through another resistive element consisting of another barrier metal film and another tungsten plug. Thus, a semiconductor device including a polydiode element which is resistant to surge or contamination is provided.

摘要翻译： 铝线通过由阻挡金属膜和钨插塞构成的电阻元件连接到多晶硅元件的P型层。 另一铝线通过由另一个阻挡金属膜和另一个钨插塞组成的另一个电阻元件连接到多晶硅元件的N型层。 因此，提供了一种包括抗电涌或污染的多极体元件的半导体器件。

公开(公告)号：US6008674A

公开(公告)日：1999-12-28

申请号：US927796

申请日：1997-09-11

申请人： Tomohisa Wada ,  Masaaki Mihara ,  Yasuhiko Taito ,  Yoshikazu Miyawaki ,  Katsumi Dosaka

发明人： Tomohisa Wada ,  Masaaki Mihara ,  Yasuhiko Taito ,  Yoshikazu Miyawaki ,  Katsumi Dosaka

IPC分类号： G11C16/06 ,  G05F1/56 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  H03K5/153

CPC分类号： G11C5/147 ,  G05F3/242

摘要： A semiconductor integrated circuit device with a high voltage detection circuit comprises a high voltage step-down circuit for stepping down a high voltage input and outputting the stepped-down voltage, a reference voltage generator for generating plural reference voltages, a reference voltage selector for selecting one of the plural reference voltages, a high voltage detection circuit for comparing the stepped down voltage with the selected reference voltage to detect a high voltage and a control circuit for controlling the voltage drop of the high voltage and selection of the plural reference voltages to set the high voltage to be detected by the high voltage detector. There is also disclosed semiconductor integrated circuit having a high voltage step-down circuit for outputting plural stepped-down voltages having a fine tuner for fine-tuning each of the plural stepped-down voltages wherein a stepped-down voltage having been tuned finely is compared with a reference voltage given by a reference voltage generator.

摘要翻译： 具有高电压检测电路的半导体集成电路装置包括用于降压高压输入并输出降压的高压降压电路，用于产生多个参考电压的参考电压发生器，用于选择的参考电压选择器 多个参考电压中的一个，用于将降压电压与所选择的参考电压进行比较以检测高电压的高电压检测电路，以及用于控制高电压的电压降和选择多个参考电压的控制电路以设置 由高电压检测器检测的高电压。 还公开了一种具有高压降压电路的半导体集成电路，用于输出具有微调整器的多个降压电压，用于微调多个降压电压中的每一个，其中比较精调的降压电压 具有由参考电压发生器给出的参考电压。

公开(公告)号：US09183346B2

公开(公告)日：2015-11-10

申请号：US13702934

申请日：2012-03-12

申请人： Masaaki Mihara

发明人： Masaaki Mihara

IPC分类号： B25J9/18 ,  G06F19/00 ,  B25J9/10 ,  B62D57/032

CPC分类号： B62D57/02 ,  B25J9/102 ,  B62D57/032 ,  G06F19/00 ,  Y10S901/23 ,  Y10T74/20317

摘要： Embodiments provided herein generally relate to robotic limbs and uses thereof. In some embodiments, a motor for driving movement of the limb is provided. In some embodiments, the motor for driving movement of the limb can itself be repositioned, thereby altering the forces and/or torque involved in moving and/or operating the limb.

摘要翻译： 本文提供的实施例通常涉及机器人肢体及其用途。 在一些实施例中，提供用于驱动肢体运动的马达。 在一些实施例中，用于驱动肢体运动的马达本身可以重新定位，从而改变在移动和/或操作肢体时涉及的力和/或扭矩。

公开(公告)号：US07969780B2

公开(公告)日：2011-06-28

申请号：US11776491

申请日：2007-07-11

申请人： Taku Ogura ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Taku Ogura ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C11/34 ,  G11C14/00

CPC分类号： G11C11/412 ,  G11C14/00 ,  G11C14/0063

摘要： An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters including memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.

摘要翻译： 本发明的目的是提供一种可以具有宽的读取余量的可重写非易失性存储单元，并且可以通过改变Vcc的电平来控制字线和位线。 作为解决方案，触发器是通过包括存储晶体管的逆变器的交叉（环路）连接形成的，所述存储器晶体管可以通过电荷注入到晶体管的侧面间隔来控制阈值电压。 在向一个存储晶体管写入数据的情况下，通过源极线将高电压提供给存储晶体管的源极，并且通过另一侧反相器的负载晶体管将高电压提供给存储晶体管的栅极。 在擦除写入数据的情况下，通过源极线将高电压提供给存储晶体管的源极。

公开(公告)号：US20090175083A1

公开(公告)日：2009-07-09

申请号：US11684035

申请日：2007-03-09

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。