公开(公告)号：US07969780B2

公开(公告)日：2011-06-28

申请号：US11776491

申请日：2007-07-11

申请人： Taku Ogura ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Taku Ogura ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C11/34 ,  G11C14/00

CPC分类号： G11C11/412 ,  G11C14/00 ,  G11C14/0063

摘要： An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters including memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.

摘要翻译： 本发明的目的是提供一种可以具有宽的读取余量的可重写非易失性存储单元，并且可以通过改变Vcc的电平来控制字线和位线。 作为解决方案，触发器是通过包括存储晶体管的逆变器的交叉（环路）连接形成的，所述存储器晶体管可以通过电荷注入到晶体管的侧面间隔来控制阈值电压。 在向一个存储晶体管写入数据的情况下，通过源极线将高电压提供给存储晶体管的源极，并且通过另一侧反相器的负载晶体管将高电压提供给存储晶体管的栅极。 在擦除写入数据的情况下，通过源极线将高电压提供给存储晶体管的源极。

公开(公告)号：US20080019162A1

公开(公告)日：2008-01-24

申请号：US11758108

申请日：2007-06-05

申请人： Taku OGURA ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Taku OGURA ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C5/06

CPC分类号： G11C11/412 ,  G11C14/00 ,  G11C14/0063

摘要： This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of the flip-flop on a side thereof. The storage transistors of the inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. This non-volatile semiconductor storage device further includes two bit lines, each of which is connected to a respective one of the two gate transistors; a word line which is connected to both of the gate electrodes of the two gate transistors; a first voltage supply line which is connected to the sources of the storage transistors of the inverters; and a second voltage supply line which is connected to the sources of the load transistors of the inverters.

摘要翻译： 这种非易失性半导体存储器件包括一个触发器，其中每个由串联连接的负载晶体管和存储晶体管组成的两个反相器是交叉连接的; 以及两个栅极晶体管，每个分别在触发器的一侧分别连接到触发器的节点。 反相器的存储晶体管由存储晶体管构成，其可以通过将电子注入其栅极附近来控制阈值电压。 该非易失性半导体存储装置还包括两个位线，每个位线连接到两个栅极晶体管中的相应一个; 连接到两个栅极晶体管的两个栅电极的字线; 连接到逆变器的存储晶体管的源极的第一电源线; 以及与逆变器的负载晶体管的源极连接的第二电压供给线。

公开(公告)号：US08000137B2

公开(公告)日：2011-08-16

申请号：US12400015

申请日：2009-03-09

申请人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

发明人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

IPC分类号： G11C16/04

CPC分类号： G11C16/045 ,  G11C16/0441 ,  G11C16/12 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558

摘要： A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

摘要翻译： 非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

公开(公告)号：US20090244972A1

公开(公告)日：2009-10-01

申请号：US12400015

申请日：2009-03-09

申请人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

发明人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

IPC分类号： G11C14/00 ,  G11C16/04 ,  G11C7/06

CPC分类号： G11C16/045 ,  G11C16/0441 ,  G11C16/12 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558

摘要： A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

摘要翻译： 非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

公开(公告)号：US20090175083A1

公开(公告)日：2009-07-09

申请号：US11684035

申请日：2007-03-09

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US07924615B2

公开(公告)日：2011-04-12

申请号：US12714750

申请日：2010-03-01

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C11/34

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US20100149875A1

公开(公告)日：2010-06-17

申请号：US12714750

申请日：2010-03-01

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及非易失性半导体存储器，更具体地说涉及具有增加的程序吞吐量的非易失性半导体存储器 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US07701778B2

公开(公告)日：2010-04-20

申请号：US11684035

申请日：2007-03-09

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C11/34

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US07254084B2

公开(公告)日：2007-08-07

申请号：US11138344

申请日：2005-05-27

申请人： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

发明人： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC分类号： G11C5/14 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

摘要： A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

公开(公告)号：US07043466B2

公开(公告)日：2006-05-09

申请号：US09739758

申请日：2000-12-20

申请人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

发明人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC分类号： G06N3/06 ,  G06N3/063 ,  G06N3/067 ,  G06N1/00 ,  G06F15/18

CPC分类号： G06N3/063

摘要： The neural network processing system according to the present invention includes a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit.

摘要翻译： 根据本发明的神经网络处理系统包括存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。